0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: UniPhier System Bus
0008
0009 description: |
0010 The UniPhier System Bus is an external bus that connects on-board devices to
0011 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
0012 some control signals. It supports up to 8 banks (chip selects).
0013
0014 Before any access to the bus, the bus controller must be configured; the bus
0015 controller registers provide the control for the translation from the offset
0016 within each bank to the CPU-viewed address. The needed setup includes the
0017 base address, the size of each bank. Optionally, some timing parameters can
0018 be optimized for faster bus access.
0019
0020 maintainers:
0021 - Masahiro Yamada <yamada.masahiro@socionext.com>
0022
0023 properties:
0024 compatible:
0025 const: socionext,uniphier-system-bus
0026
0027 reg:
0028 maxItems: 1
0029
0030 "#address-cells":
0031 description: |
0032 The first cell is the bank number (chip select).
0033 The second cell is the address offset within the bank.
0034 const: 2
0035
0036 "#size-cells":
0037 const: 1
0038
0039 ranges:
0040 description: |
0041 Provide address translation from the System Bus to the parent bus.
0042
0043 Note:
0044 The address region(s) that can be assigned for the System Bus is
0045 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
0046 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
0047 There might be additional limitations depending on SoCs and the boot mode.
0048 The address translation is arbitrary as long as the banks are assigned in
0049 the supported address space with the required alignment and they do not
0050 overlap one another.
0051
0052 For example, it is possible to map:
0053 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
0054 It is also possible to map:
0055 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
0056 There is no reason to stick to a particular translation mapping, but the
0057 "ranges" property should provide a "reasonable" default that is known to
0058 work. The software should initialize the bus controller according to it.
0059
0060 patternProperties:
0061 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
0062 description: Devices attached to chip selects
0063 type: object
0064
0065 required:
0066 - compatible
0067 - reg
0068 - "#address-cells"
0069 - "#size-cells"
0070 - ranges
0071
0072 additionalProperties: false
0073
0074 examples:
0075 - |
0076 // In this example,
0077 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
0078 // mapped to 0x43f00000 of the parent bus.
0079 // - the UART device is connected at the offset 0x00200000 of CS5 and
0080 // mapped to 0x46200000 of the parent bus.
0081
0082 system-bus@58c00000 {
0083 compatible = "socionext,uniphier-system-bus";
0084 reg = <0x58c00000 0x400>;
0085 #address-cells = <2>;
0086 #size-cells = <1>;
0087 ranges = <1 0x00000000 0x42000000 0x02000000>,
0088 <5 0x00000000 0x46000000 0x01000000>;
0089
0090 ethernet@1,1f00000 {
0091 compatible = "smsc,lan9115";
0092 reg = <1 0x01f00000 0x1000>;
0093 interrupts = <0 48 4>;
0094 phy-mode = "mii";
0095 };
0096
0097 serial@5,200000 {
0098 compatible = "ns16550a";
0099 reg = <5 0x00200000 0x20>;
0100 interrupts = <0 49 4>;
0101 clock-frequency = <12288000>;
0102 };
0103 };
