0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
0008
0009 maintainers:
0010 - Michael Srba <Michael.Srba@seznam.cz>
0011
0012 description: |
0013 This binding describes the dependencies (clocks, resets, power domains) which
0014 need to be turned on in a sequence before communication over the AHB bus
0015 becomes possible.
0016
0017 Additionally, the reg property is used to pass to the driver the location of
0018 two sadly undocumented registers which need to be poked as part of the sequence.
0019
0020 The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
0021 controllers, a hexagon core, and a clock controller which provides clocks for
0022 the above.
0023
0024 properties:
0025 compatible:
0026 items:
0027 - const: qcom,msm8998-ssc-block-bus
0028 - const: qcom,ssc-block-bus
0029
0030 reg:
0031 items:
0032 - description: SSCAON_CONFIG0 registers
0033 - description: SSCAON_CONFIG1 registers
0034
0035 reg-names:
0036 items:
0037 - const: mpm_sscaon_config0
0038 - const: mpm_sscaon_config1
0039
0040 '#address-cells':
0041 enum: [ 1, 2 ]
0042
0043 '#size-cells':
0044 enum: [ 1, 2 ]
0045
0046 ranges: true
0047
0048 clocks:
0049 maxItems: 6
0050
0051 clock-names:
0052 items:
0053 - const: xo
0054 - const: aggre2
0055 - const: gcc_im_sleep
0056 - const: aggre2_north
0057 - const: ssc_xo
0058 - const: ssc_ahbs
0059
0060 power-domains:
0061 items:
0062 - description: CX power domain
0063 - description: MX power domain
0064
0065 power-domain-names:
0066 items:
0067 - const: ssc_cx
0068 - const: ssc_mx
0069
0070 resets:
0071 items:
0072 - description: Main reset
0073 - description:
0074 SSC Branch Control Register reset (associated with the ssc_xo and
0075 ssc_ahbs clocks)
0076
0077 reset-names:
0078 items:
0079 - const: ssc_reset
0080 - const: ssc_bcr
0081
0082 qcom,halt-regs:
0083 $ref: /schemas/types.yaml#/definitions/phandle-array
0084 description: describes how to locate the ssc AXI halt register
0085 items:
0086 - items:
0087 - description: Phandle reference to a syscon representing TCSR
0088 - description: offset for the ssc AXI halt register
0089
0090 required:
0091 - compatible
0092 - reg
0093 - reg-names
0094 - '#address-cells'
0095 - '#size-cells'
0096 - ranges
0097 - clocks
0098 - clock-names
0099 - power-domains
0100 - power-domain-names
0101 - resets
0102 - reset-names
0103 - qcom,halt-regs
0104
0105 additionalProperties:
0106 type: object
0107
0108 examples:
0109 - |
0110 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
0111 #include <dt-bindings/clock/qcom,rpmcc.h>
0112 #include <dt-bindings/power/qcom-rpmpd.h>
0113
0114 soc {
0115 #address-cells = <1>;
0116 #size-cells = <1>;
0117
0118 // devices under this node are physically located in the SSC block, connected to an ssc-internal bus;
0119 ssc_ahb_slave: bus@10ac008 {
0120 #address-cells = <1>;
0121 #size-cells = <1>;
0122 ranges;
0123
0124 compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus";
0125 reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
0126 reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
0127
0128 clocks = <&xo>,
0129 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
0130 <&gcc GCC_IM_SLEEP>,
0131 <&gcc AGGRE2_SNOC_NORTH_AXI>,
0132 <&gcc SSC_XO>,
0133 <&gcc SSC_CNOC_AHBS_CLK>;
0134 clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
0135
0136 resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;
0137 reset-names = "ssc_reset", "ssc_bcr";
0138
0139 power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
0140 power-domain-names = "ssc_cx", "ssc_mx";
0141
0142 qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
0143 };
0144 };
