0001 Qualcomm External Bus Interface 2 (EBI2)
0002
0003 The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
0004 external memory (such as NAND or other memory-mapped peripherals) whereas
0005 LCDC handles LCD displays.
0006
0007 As it says it connects devices to an external bus interface, meaning address
0008 lines (up to 9 address lines so can only address 1KiB external memory space),
0009 data lines (16 bits), OE (output enable), ADV (address valid, used on some
0010 NOR flash memories), WE (write enable). This on top of 6 different chip selects
0011 (CS0 thru CS5) so that in theory 6 different devices can be connected.
0012
0013 Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
0014 and the bus can only come out on these pins, however if some of the pins are
0015 unused they can be left unconnected or remuxed to be used as GPIO or in some
0016 cases other orthogonal functions as well.
0017
0018 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
0019
0020 The chip selects have the following memory range assignments. This region of
0021 memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
0022
0023 Chip Select Physical address base
0024 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
0025 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
0026 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
0027 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
0028 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
0029 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
0030
0031 The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
0032 August 6, 2012 contains some incomplete documentation of the EBI2.
0033
0034 FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
0035 We have not been able to figure out which bit fields these correspond to
0036 in the hardware, or what valid values exist. The current hypothesis is that
0037 this is something just used on the FAST chip selects and that the SLOW
0038 chip selects are understood fully. There is also a "byte device enable"
0039 flag somewhere for 8bit memories.
0040
0041 FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
0042 unclear what this means, if they are mutually exclusive or can be used
0043 together, or if some chip selects are hardwired to be FAST and others are SLOW
0044 by design.
0045
0046 The XMEM registers are totally undocumented but could be partially decoded
0047 because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
0048 similar register layout, see: http://www.cypress.com/file/105771/download
0049
0050 Required properties:
0051 - compatible: should be one of:
0052 "qcom,msm8660-ebi2"
0053 "qcom,apq8060-ebi2"
0054 - #address-cells: should be <2>: the first cell is the chipselect,
0055 the second cell is the offset inside the memory range
0056 - #size-cells: should be <1>
0057 - ranges: should be set to:
0058 ranges = <0 0x0 0x1a800000 0x00800000>,
0059 <1 0x0 0x1b000000 0x00800000>,
0060 <2 0x0 0x1b800000 0x00800000>,
0061 <3 0x0 0x1d000000 0x08000000>,
0062 <4 0x0 0x1c800000 0x00800000>,
0063 <5 0x0 0x1c000000 0x00800000>;
0064 - reg: two ranges of registers: EBI2 config and XMEM config areas
0065 - reg-names: should be "ebi2", "xmem"
0066 - clocks: two clocks, EBI_2X and EBI
0067 - clock-names: should be "ebi2x", "ebi2"
0068
0069 Optional subnodes:
0070 - Nodes inside the EBI2 will be considered device nodes.
0071
0072 The following optional properties are properties that can be tagged onto
0073 any device subnode. We are assuming that there can be only ONE device per
0074 chipselect subnode, else the properties will become ambiguous.
0075
0076 Optional properties arrays for SLOW chip selects:
0077 - qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
0078 drive the data bus after OE is de-asserted, in order to avoid contention on
0079 the data bus. They are inserted when reading one CS and switching to another
0080 CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum
0081 value is actually 1, so a value of 0 will still yield 1 recovery cycle.
0082 - qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
0083 inserted after every write minimum 1. The data out is driven from the time
0084 WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS
0085 stays active for 1 extra cycle etc. Valid values 0 thru 15.
0086 - qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
0087 the first write to a page or burst memory. Valid values 0 thru 255.
0088 - qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
0089 first read to a page or burst memory. Valid values 0 thru 255.
0090 - qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
0091 cycle. Valid values 0 thru 15.
0092 - qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
0093 cycle. Valid values 0 thru 15.
0094
0095 Optional properties arrays for FAST chip selects:
0096 - qcom,xmem-address-hold-enable: this is a boolean property stating that we
0097 shall hold the address for an extra cycle to meet hold time requirements
0098 with ADV assertion.
0099 - qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
0100 assertion, with respect to the cycle where ADV (address valid) is asserted.
0101 2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
0102 - qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
0103 read transfer. For a single read transfer this will be the time from CS
0104 assertion to OE assertion. Valid values 0 thru 15.
0105
0106
0107 Example:
0108
0109 ebi2@1a100000 {
0110 compatible = "qcom,apq8060-ebi2";
0111 #address-cells = <2>;
0112 #size-cells = <1>;
0113 ranges = <0 0x0 0x1a800000 0x00800000>,
0114 <1 0x0 0x1b000000 0x00800000>,
0115 <2 0x0 0x1b800000 0x00800000>,
0116 <3 0x0 0x1d000000 0x08000000>,
0117 <4 0x0 0x1c800000 0x00800000>,
0118 <5 0x0 0x1c000000 0x00800000>;
0119 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
0120 reg-names = "ebi2", "xmem";
0121 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
0122 clock-names = "ebi2x", "ebi2";
0123 /* Make sure to set up the pin control for the EBI2 */
0124 pinctrl-names = "default";
0125 pinctrl-0 = <&foo_ebi2_pins>;
0126
0127 foo-ebi2@2,0 {
0128 compatible = "foo";
0129 reg = <2 0x0 0x100>;
0130 (...)
0131 qcom,xmem-recovery-cycles = <0>;
0132 qcom,xmem-write-hold-cycles = <3>;
0133 qcom,xmem-write-delta-cycles = <31>;
0134 qcom,xmem-read-delta-cycles = <28>;
0135 qcom,xmem-write-wait-cycles = <9>;
0136 qcom,xmem-read-wait-cycles = <9>;
0137 };
0138 };
