0001 Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
0002
0003 The Generic Memory Interface bus enables memory transfers between internal and
0004 external memory. Can be used to attach various high speed devices such as
0005 synchronous/asynchronous NOR, FPGA, UARTS and more.
0006
0007 The actual devices are instantiated from the child nodes of a GMI node.
0008
0009 Required properties:
0010 - compatible : Should contain one of the following:
0011 For Tegra20 must contain "nvidia,tegra20-gmi".
0012 For Tegra30 must contain "nvidia,tegra30-gmi".
0013 - reg: Should contain GMI controller registers location and length.
0014 - clocks: Must contain an entry for each entry in clock-names.
0015 - clock-names: Must include the following entries: "gmi"
0016 - resets : Must contain an entry for each entry in reset-names.
0017 - reset-names : Must include the following entries: "gmi"
0018 - #address-cells: The number of cells used to represent physical base
0019 addresses in the GMI address space. Should be 2.
0020 - #size-cells: The number of cells used to represent the size of an address
0021 range in the GMI address space. Should be 1.
0022 - ranges: Must be set up to reflect the memory layout with three integer values
0023 for each chip-select line in use (only one entry is supported, see below
0024 comments):
0025 <cs-number> <offset> <physical address of mapping> <size>
0026
0027 Note that the GMI controller does not have any internal chip-select address
0028 decoding, because of that chip-selects either need to be managed via software
0029 or by employing external chip-select decoding logic.
0030
0031 If external chip-select logic is used to support multiple devices it is assumed
0032 that the devices use the same timing and so are probably the same type. It also
0033 assumes that they can fit in the 256MB address range. In this case only one
0034 child device is supported which represents the active chip-select line, see
0035 examples for more insight.
0036
0037 The chip-select number is decoded from the child nodes second address cell of
0038 'ranges' property, if 'ranges' property is not present or empty chip-select will
0039 then be decoded from the first cell of the 'reg' property.
0040
0041 Optional child cs node properties:
0042
0043 - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit.
0044 - nvidia,snor-mux-mode: Enable address/data MUX mode.
0045 - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data.
0046 If omitted it will be asserted with data.
0047 - nvidia,snor-rdy-active-high: RDY signal is active high
0048 - nvidia,snor-adv-active-high: ADV signal is active high
0049 - nvidia,snor-oe-active-high: WE/OE signal is active high
0050 - nvidia,snor-cs-active-high: CS signal is active high
0051
0052 Note that there is some special handling for the timing values.
0053 From Tegra TRM:
0054 Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1
0055
0056 - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
0057 bus. Valid values are 0-15, default is 1
0058 - nvidia,snor-hold-width: Number of cycles CE stays asserted after the
0059 de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N
0060 (in case of MASTER Request). Valid values are 0-15, default is 1
0061 - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
0062 Valid values are 0-15, default is 1.
0063 - nvidia,snor-ce-width: Number of cycles before CE is asserted.
0064 Valid values are 0-15, default is 4
0065 - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
0066 Valid values are 0-15, default is 1
0067 - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
0068 Valid values are 0-255, default is 1
0069 - nvidia,snor-wait-width: Number of cycles before READY is asserted.
0070 Valid values are 0-255, default is 3
0071
0072 Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
0073 controllers with a simple-bus node since they are all connected to the same
0074 chip-select (CS4), in this example external address decoding is provided:
0075
0076 gmi@70009000 {
0077 compatible = "nvidia,tegra20-gmi";
0078 reg = <0x70009000 0x1000>;
0079 #address-cells = <2>;
0080 #size-cells = <1>;
0081 clocks = <&tegra_car TEGRA20_CLK_NOR>;
0082 clock-names = "gmi";
0083 resets = <&tegra_car 42>;
0084 reset-names = "gmi";
0085 ranges = <4 0 0xd0000000 0xfffffff>;
0086
0087 bus@4,0 {
0088 compatible = "simple-bus";
0089 #address-cells = <1>;
0090 #size-cells = <1>;
0091 ranges = <0 4 0 0x40100>;
0092
0093 nvidia,snor-mux-mode;
0094 nvidia,snor-adv-active-high;
0095
0096 can@0 {
0097 reg = <0 0x100>;
0098 ...
0099 };
0100
0101 can@40000 {
0102 reg = <0x40000 0x100>;
0103 ...
0104 };
0105 };
0106 };
0107
0108 Example with one SJA1000 CAN controller connected to the GMI bus
0109 on CS4:
0110
0111 gmi@70009000 {
0112 compatible = "nvidia,tegra20-gmi";
0113 reg = <0x70009000 0x1000>;
0114 #address-cells = <2>;
0115 #size-cells = <1>;
0116 clocks = <&tegra_car TEGRA20_CLK_NOR>;
0117 clock-names = "gmi";
0118 resets = <&tegra_car 42>;
0119 reset-names = "gmi";
0120 ranges = <4 0 0xd0000000 0xfffffff>;
0121
0122 can@4,0 {
0123 reg = <4 0 0x100>;
0124 nvidia,snor-mux-mode;
0125 nvidia,snor-adv-active-high;
0126 ...
0127 };
0128 };
