0001
0002 * Marvell MBus
0003
0004 Required properties:
0005
0006 - compatible: Should be set to one of the following:
0007 marvell,armada370-mbus
0008 marvell,armadaxp-mbus
0009 marvell,armada375-mbus
0010 marvell,armada380-mbus
0011 marvell,kirkwood-mbus
0012 marvell,dove-mbus
0013 marvell,orion5x-88f5281-mbus
0014 marvell,orion5x-88f5182-mbus
0015 marvell,orion5x-88f5181-mbus
0016 marvell,orion5x-88f6183-mbus
0017 marvell,mv78xx0-mbus
0018
0019 - address-cells: Must be '2'. The first cell for the MBus ID encoding,
0020 the second cell for the address offset within the window.
0021
0022 - size-cells: Must be '1'.
0023
0024 - ranges: Must be set up to provide a proper translation for each child.
0025 See the examples below.
0026
0027 - controller: Contains a single phandle referring to the MBus controller
0028 node. This allows to specify the node that contains the
0029 registers that control the MBus, which is typically contained
0030 within the internal register window (see below).
0031
0032 Optional properties:
0033
0034 - pcie-mem-aperture: This optional property contains the aperture for
0035 the memory region of the PCIe driver.
0036 If it's defined, it must encode the base address and
0037 size for the address decoding windows allocated for
0038 the PCIe memory region.
0039
0040 - pcie-io-aperture: Just as explained for the above property, this
0041 optional property contains the aperture for the
0042 I/O region of the PCIe driver.
0043
0044 * Marvell MBus controller
0045
0046 Required properties:
0047
0048 - compatible: Should be set to "marvell,mbus-controller".
0049
0050 - reg: Device's register space.
0051 Two or three entries are expected (see the examples below):
0052 the first one controls the devices decoding window,
0053 the second one controls the SDRAM decoding window and
0054 the third controls the MBus bridge (only with the
0055 marvell,armada370-mbus and marvell,armadaxp-mbus
0056 compatible strings)
0057
0058 Example:
0059
0060 soc {
0061 compatible = "marvell,armada370-mbus", "simple-bus";
0062 #address-cells = <2>;
0063 #size-cells = <1>;
0064 controller = <&mbusc>;
0065 pcie-mem-aperture = <0xe0000000 0x8000000>;
0066 pcie-io-aperture = <0xe8000000 0x100000>;
0067
0068 internal-regs {
0069 compatible = "simple-bus";
0070
0071 mbusc: mbus-controller@20000 {
0072 compatible = "marvell,mbus-controller";
0073 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
0074 };
0075
0076 /* more children ...*/
0077 };
0078 };
0079
0080 ** MBus address decoding window specification
0081
0082 The MBus children address space is comprised of two cells: the first one for
0083 the window ID and the second one for the offset within the window.
0084 In order to allow to describe valid and non-valid window entries, the
0085 following encoding is used:
0086
0087 0xSIAA0000 0x00oooooo
0088
0089 Where:
0090
0091 S = 0x0 for a MBus valid window
0092 S = 0xf for a non-valid window (see below)
0093
0094 If S = 0x0, then:
0095
0096 I = 4-bit window target ID
0097 AA = windpw attribute
0098
0099 If S = 0xf, then:
0100
0101 I = don't care
0102 AA = 1 for internal register
0103
0104 Following the above encoding, for each ranges entry for a MBus valid window
0105 (S = 0x0), an address decoding window is allocated. On the other side,
0106 entries for translation that do not correspond to valid windows (S = 0xf)
0107 are skipped.
0108
0109 soc {
0110 compatible = "marvell,armada370-mbus", "simple-bus";
0111 #address-cells = <2>;
0112 #size-cells = <1>;
0113 controller = <&mbusc>;
0114
0115 ranges = <0xf0010000 0 0 0xd0000000 0x100000
0116 0x01e00000 0 0 0xfff00000 0x100000>;
0117
0118 bootrom {
0119 compatible = "marvell,bootrom";
0120 reg = <0x01e00000 0 0x100000>;
0121 };
0122
0123 /* other children */
0124 ...
0125
0126 internal-regs {
0127 compatible = "simple-bus";
0128 ranges = <0 0xf0010000 0 0x100000>;
0129
0130 mbusc: mbus-controller@20000 {
0131 compatible = "marvell,mbus-controller";
0132 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
0133 };
0134
0135 /* more children ...*/
0136 };
0137 };
0138
0139 In the shown example, the translation entry in the 'ranges' property is what
0140 makes the MBus driver create a static decoding window for the corresponding
0141 given child device. Note that the binding does not require child nodes to be
0142 present. Of course, child nodes are needed to probe the devices.
0143
0144 Since each window is identified by its target ID and attribute ID there's
0145 a special macro that can be use to simplify the translation entries:
0146
0147 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
0148
0149 Using this macro, the above example would be:
0150
0151 soc {
0152 compatible = "marvell,armada370-mbus", "simple-bus";
0153 #address-cells = <2>;
0154 #size-cells = <1>;
0155 controller = <&mbusc>;
0156
0157 ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
0158 MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;
0159
0160 bootrom {
0161 compatible = "marvell,bootrom";
0162 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
0163 };
0164
0165 /* other children */
0166 ...
0167
0168 internal-regs {
0169 compatible = "simple-bus";
0170 #address-cells = <1>;
0171 #size-cells = <1>;
0172 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
0173
0174 mbusc: mbus-controller@20000 {
0175 compatible = "marvell,mbus-controller";
0176 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
0177 };
0178
0179 /* other children */
0180 ...
0181 };
0182 };
0183
0184
0185 ** About the window base address
0186
0187 Remember the MBus controller allows a great deal of flexibility for choosing
0188 the decoding window base address. When planning the device tree layout it's
0189 possible to choose any address as the base address, provided of course there's
0190 a region large enough available, and with the required alignment.
0191
0192 Yet in other words: there's nothing preventing us from setting a base address
0193 of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
0194 unused.
0195
0196 ** Window allocation policy
0197
0198 The mbus-node ranges property defines a set of mbus windows that are expected
0199 to be set by the operating system and that are guaranteed to be free of overlaps
0200 with one another or with the system memory ranges.
0201
0202 Each entry in the property refers to exactly one window. If the operating system
0203 chooses to use a different set of mbus windows, it must ensure that any address
0204 translations performed from downstream devices are adapted accordingly.
0205
0206 The operating system may insert additional mbus windows that do not conflict
0207 with the ones listed in the ranges, e.g. for mapping PCIe devices.
0208 As a special case, the internal register window must be set up by the boot
0209 loader at the address listed in the ranges property, since access to that region
0210 is needed to set up the other windows.
0211
0212 ** Example
0213
0214 See the example below, where a more complete device tree is shown:
0215
0216 soc {
0217 compatible = "marvell,armadaxp-mbus", "simple-bus";
0218 controller = <&mbusc>;
0219
0220 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
0221 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
0222 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
0223
0224 bootrom {
0225 compatible = "marvell,bootrom";
0226 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
0227 };
0228
0229 devbus-bootcs {
0230 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
0231
0232 /* NOR */
0233 nor {
0234 compatible = "cfi-flash";
0235 reg = <0 0x8000000>;
0236 bank-width = <2>;
0237 };
0238 };
0239
0240 pcie-controller {
0241 compatible = "marvell,armada-xp-pcie";
0242 device_type = "pci";
0243
0244 #address-cells = <3>;
0245 #size-cells = <2>;
0246
0247 ranges =
0248 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0249 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0250 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0251 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0252 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0253 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
0254 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
0255
0256
0257 pcie@1,0 {
0258 /* Port 0, Lane 0 */
0259 };
0260 };
0261
0262 internal-regs {
0263 compatible = "simple-bus";
0264 #address-cells = <1>;
0265 #size-cells = <1>;
0266 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
0267
0268 mbusc: mbus-controller@20000 {
0269 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
0270 };
0271
0272 interrupt-controller@20000 {
0273 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
0274 };
0275 };
0276 };
