0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Intel IXP4xx Expansion Bus Controller
0008
0009 description: |
0010 The IXP4xx expansion bus controller handles access to devices on the
0011 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
0012 including IXP42x, IXP43x, IXP45x and IXP46x.
0013
0014 maintainers:
0015 - Linus Walleij <linus.walleij@linaro.org>
0016
0017 properties:
0018 $nodename:
0019 pattern: '^bus@[0-9a-f]+$'
0020
0021 compatible:
0022 items:
0023 - enum:
0024 - intel,ixp42x-expansion-bus-controller
0025 - intel,ixp43x-expansion-bus-controller
0026 - intel,ixp45x-expansion-bus-controller
0027 - intel,ixp46x-expansion-bus-controller
0028 - const: syscon
0029
0030 reg:
0031 description: Control registers for the expansion bus, these are not
0032 inside the memory range handled by the expansion bus.
0033 maxItems: 1
0034
0035 native-endian:
0036 $ref: /schemas/types.yaml#/definitions/flag
0037 description: The IXP4xx has a peculiar MMIO access scheme, as it changes
0038 the access pattern for words (swizzling) on the bus depending on whether
0039 the SoC is running in big-endian or little-endian mode. Thus the
0040 registers must always be accessed using native endianness.
0041
0042 "#address-cells":
0043 description: |
0044 The first cell is the chip select number.
0045 The second cell is the address offset within the bank.
0046 const: 2
0047
0048 "#size-cells":
0049 const: 1
0050
0051 ranges: true
0052 dma-ranges: true
0053
0054 patternProperties:
0055 "^.*@[0-7],[0-9a-f]+$":
0056 description: Devices attached to chip selects are represented as
0057 subnodes.
0058 type: object
0059
0060 properties:
0061 intel,ixp4xx-eb-t1:
0062 description: Address timing, extend address phase with n cycles.
0063 $ref: /schemas/types.yaml#/definitions/uint32
0064 maximum: 3
0065
0066 intel,ixp4xx-eb-t2:
0067 description: Setup chip select timing, extend setup phase with n cycles.
0068 $ref: /schemas/types.yaml#/definitions/uint32
0069 maximum: 3
0070
0071 intel,ixp4xx-eb-t3:
0072 description: Strobe timing, extend strobe phase with n cycles.
0073 $ref: /schemas/types.yaml#/definitions/uint32
0074 maximum: 15
0075
0076 intel,ixp4xx-eb-t4:
0077 description: Hold timing, extend hold phase with n cycles.
0078 $ref: /schemas/types.yaml#/definitions/uint32
0079 maximum: 3
0080
0081 intel,ixp4xx-eb-t5:
0082 description: Recovery timing, extend recovery phase with n cycles.
0083 $ref: /schemas/types.yaml#/definitions/uint32
0084 maximum: 15
0085
0086 intel,ixp4xx-eb-cycle-type:
0087 description: The type of cycles to use on the expansion bus for this
0088 chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
0089 $ref: /schemas/types.yaml#/definitions/uint32
0090 enum: [0, 1, 2]
0091
0092 intel,ixp4xx-eb-byte-access-on-halfword:
0093 description: Allow byte read access on half word devices.
0094 $ref: /schemas/types.yaml#/definitions/uint32
0095 enum: [0, 1]
0096
0097 intel,ixp4xx-eb-hpi-hrdy-pol-high:
0098 description: Set HPI HRDY polarity to active high when using HPI.
0099 $ref: /schemas/types.yaml#/definitions/uint32
0100 enum: [0, 1]
0101
0102 intel,ixp4xx-eb-mux-address-and-data:
0103 description: Multiplex address and data on the data bus.
0104 $ref: /schemas/types.yaml#/definitions/uint32
0105 enum: [0, 1]
0106
0107 intel,ixp4xx-eb-ahb-split-transfers:
0108 description: Enable AHB split transfers.
0109 $ref: /schemas/types.yaml#/definitions/uint32
0110 enum: [0, 1]
0111
0112 intel,ixp4xx-eb-write-enable:
0113 description: Enable write cycles.
0114 $ref: /schemas/types.yaml#/definitions/uint32
0115 enum: [0, 1]
0116
0117 intel,ixp4xx-eb-byte-access:
0118 description: Expansion bus uses only 8 bits. The default is to use
0119 16 bits.
0120 $ref: /schemas/types.yaml#/definitions/uint32
0121 enum: [0, 1]
0122
0123 required:
0124 - compatible
0125 - reg
0126 - native-endian
0127 - "#address-cells"
0128 - "#size-cells"
0129 - ranges
0130 - dma-ranges
0131
0132 additionalProperties: false
0133
0134 examples:
0135 - |
0136 #include <dt-bindings/interrupt-controller/irq.h>
0137 bus@50000000 {
0138 compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
0139 reg = <0xc4000000 0x28>;
0140 native-endian;
0141 #address-cells = <2>;
0142 #size-cells = <1>;
0143 ranges = <0 0x0 0x50000000 0x01000000>,
0144 <1 0x0 0x51000000 0x01000000>;
0145 dma-ranges = <0 0x0 0x50000000 0x01000000>,
0146 <1 0x0 0x51000000 0x01000000>;
0147 flash@0,0 {
0148 compatible = "intel,ixp4xx-flash", "cfi-flash";
0149 bank-width = <2>;
0150 reg = <0 0x00000000 0x1000000>;
0151 intel,ixp4xx-eb-t3 = <3>;
0152 intel,ixp4xx-eb-cycle-type = <0>;
0153 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
0154 intel,ixp4xx-eb-write-enable = <1>;
0155 intel,ixp4xx-eb-byte-access = <0>;
0156 };
0157 serial@1,0 {
0158 compatible = "exar,xr16l2551", "ns8250";
0159 reg = <1 0x00000000 0x10>;
0160 interrupt-parent = <&gpio0>;
0161 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
0162 clock-frequency = <1843200>;
0163 intel,ixp4xx-eb-t3 = <3>;
0164 intel,ixp4xx-eb-cycle-type = <1>;
0165 intel,ixp4xx-eb-write-enable = <1>;
0166 intel,ixp4xx-eb-byte-access = <1>;
0167 };
0168 };
