0001 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
0002
0003 Required properties:
0004
0005 - compatible : brcm,bus-axi
0006
0007 - reg : iomem address range of chipcommon core
0008
0009 The cores on the AXI bus are automatically detected by bcma with the
0010 memory ranges they are using and they get registered afterwards.
0011 Automatic detection of the IRQ number is not working on
0012 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
0013 them manually through device tree. Use an interrupt-map to specify the
0014 IRQ used by the devices on the bus. The first address is just an index,
0015 because we do not have any special register.
0016
0017 The top-level axi bus may contain children representing attached cores
0018 (devices). This is needed since some hardware details can't be auto
0019 detected (e.g. IRQ numbers). Also some of the cores may be responsible
0020 for extra things, e.g. ChipCommon providing access to the GPIO chip.
0021
0022 Example:
0023
0024 axi@18000000 {
0025 compatible = "brcm,bus-axi";
0026 reg = <0x18000000 0x1000>;
0027 ranges = <0x00000000 0x18000000 0x00100000>;
0028 #address-cells = <1>;
0029 #size-cells = <1>;
0030 #interrupt-cells = <1>;
0031 interrupt-map-mask = <0x000fffff 0xffff>;
0032 interrupt-map =
0033 /* Ethernet Controller 0 */
0034 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
0035
0036 /* Ethernet Controller 1 */
0037 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
0038
0039 /* PCIe Controller 0 */
0040 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
0041 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
0042 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
0043 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
0044 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
0045 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
0046
0047 chipcommon {
0048 reg = <0x00000000 0x1000>;
0049
0050 gpio-controller;
0051 #gpio-cells = <2>;
0052 };
0053 };
