0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Baikal-T1 AXI-bus
0009
0010 maintainers:
0011 - Serge Semin <fancer.lancer@gmail.com>
0012
0013 description: |
0014 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
0015 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
0016 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
0017 called AXI Main Interconnect) routing IO requests from one block to
0018 another: from CPU to SoC peripherals and between some SoC peripherals
0019 (mostly between peripheral devices and RAM, but also between DMA and
0020 some peripherals). In case of any protocol error, device not responding
0021 an IRQ is raised and a faulty situation is reported to the AXI EHB
0022 (Errors Handler Block) embedded on top of the DW AXI Interconnect and
0023 accessible by means of the Baikal-T1 System Controller.
0024
0025 allOf:
0026 - $ref: /schemas/simple-bus.yaml#
0027
0028 properties:
0029 compatible:
0030 contains:
0031 const: baikal,bt1-axi
0032
0033 reg:
0034 minItems: 1
0035 items:
0036 - description: Synopsys DesignWare AXI Interconnect QoS registers
0037 - description: AXI EHB MMIO system controller registers
0038
0039 reg-names:
0040 minItems: 1
0041 items:
0042 - const: qos
0043 - const: ehb
0044
0045 '#interconnect-cells':
0046 const: 1
0047
0048 syscon:
0049 $ref: /schemas/types.yaml#/definitions/phandle
0050 description: Phandle to the Baikal-T1 System Controller DT node
0051
0052 interrupts:
0053 maxItems: 1
0054
0055 clocks:
0056 items:
0057 - description: Main Interconnect uplink reference clock
0058
0059 clock-names:
0060 items:
0061 - const: aclk
0062
0063 resets:
0064 items:
0065 - description: Main Interconnect reset line
0066
0067 reset-names:
0068 items:
0069 - const: arst
0070
0071 unevaluatedProperties: false
0072
0073 required:
0074 - compatible
0075 - reg
0076 - reg-names
0077 - syscon
0078 - interrupts
0079 - clocks
0080 - clock-names
0081
0082 examples:
0083 - |
0084 #include <dt-bindings/interrupt-controller/mips-gic.h>
0085
0086 bus@1f05a000 {
0087 compatible = "baikal,bt1-axi", "simple-bus";
0088 reg = <0x1f05a000 0x1000>,
0089 <0x1f04d110 0x8>;
0090 reg-names = "qos", "ehb";
0091 #address-cells = <1>;
0092 #size-cells = <1>;
0093 #interconnect-cells = <1>;
0094
0095 syscon = <&syscon>;
0096
0097 ranges;
0098
0099 interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>;
0100
0101 clocks = <&ccu_axi 0>;
0102 clock-names = "aclk";
0103
0104 resets = <&ccu_axi 0>;
0105 reset-names = "arst";
0106 };
0107 ...
