0001 ST-Ericsson Ux500 boards
0002 ------------------------
0003
0004 Required properties (in root node) one of these:
0005 compatible = "st-ericsson,mop500" (legacy)
0006 compatible = "st-ericsson,u8500"
0007
0008 Required node (under root node):
0009
0010 soc: represents the system-on-chip and contains the chip
0011 peripherals
0012
0013 Required property of soc node, one of these:
0014 compatible = "stericsson,db8500"
0015
0016 Required subnodes under soc node:
0017
0018 backupram: (used for CPU spin tables and for storing data
0019 during retention, system won't boot without this):
0020 compatible = "ste,dbx500-backupram"
0021
0022 scu:
0023 see binding for arm/arm,scu.yaml
0024
0025 interrupt-controller:
0026 see binding for interrupt-controller/arm,gic.txt
0027
0028 timer:
0029 see binding for timer/arm,twd-timer.yaml
0030
0031 clocks:
0032 see binding for clocks/ux500.txt
0033
0034 Example:
0035
0036 /dts-v1/;
0037
0038 / {
0039 model = "ST-Ericsson HREF (pre-v60) and ST UIB";
0040 compatible = "st-ericsson,mop500", "st-ericsson,u8500";
0041
0042 soc {
0043 #address-cells = <1>;
0044 #size-cells = <1>;
0045 compatible = "stericsson,db8500";
0046 interrupt-parent = <&intc>;
0047 ranges;
0048
0049 backupram@80150000 {
0050 compatible = "ste,dbx500-backupram";
0051 reg = <0x80150000 0x2000>;
0052 };
0053
0054 intc: interrupt-controller@a0411000 {
0055 compatible = "arm,cortex-a9-gic";
0056 #interrupt-cells = <3>;
0057 #address-cells = <1>;
0058 interrupt-controller;
0059 reg = <0xa0411000 0x1000>,
0060 <0xa0410100 0x100>;
0061 };
0062
0063 scu@a0410000 {
0064 compatible = "arm,cortex-a9-scu";
0065 reg = <0xa0410000 0x100>;
0066 };
0067
0068 timer@a0410600 {
0069 compatible = "arm,cortex-a9-twd-timer";
0070 reg = <0xa0410600 0x20>;
0071 interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
0072 clocks = <&smp_twd_clk>;
0073 };
0074
0075 clocks {
0076 compatible = "stericsson,u8500-clks";
0077
0078 smp_twd_clk: smp-twd-clock {
0079 #clock-cells = <0>;
0080 };
0081 };
0082 };
0083 };
