0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Tegra Power Management Controller (PMC)
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jonathan Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014 compatible:
0015 enum:
0016 - nvidia,tegra20-pmc
0017 - nvidia,tegra30-pmc
0018 - nvidia,tegra114-pmc
0019 - nvidia,tegra124-pmc
0020 - nvidia,tegra210-pmc
0021
0022 reg:
0023 maxItems: 1
0024 description:
0025 Offset and length of the register set for the device.
0026
0027 clock-names:
0028 items:
0029 - const: pclk
0030 - const: clk32k_in
0031 description:
0032 Must includes entries pclk and clk32k_in.
0033 pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
0034 input to Tegra.
0035
0036 clocks:
0037 maxItems: 2
0038 description:
0039 Must contain an entry for each entry in clock-names.
0040 See ../clocks/clocks-bindings.txt for details.
0041
0042 '#clock-cells':
0043 const: 1
0044 description:
0045 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
0046 PMC also has blink control which allows 32Khz clock output to
0047 Tegra blink pad.
0048 Consumer of PMC clock should specify the desired clock by having
0049 the clock ID in its "clocks" phandle cell with pmc clock provider.
0050 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
0051 clock IDs.
0052
0053 '#interrupt-cells':
0054 const: 2
0055 description:
0056 Specifies number of cells needed to encode an interrupt source.
0057 The value must be 2.
0058
0059 interrupt-controller: true
0060
0061 nvidia,invert-interrupt:
0062 $ref: /schemas/types.yaml#/definitions/flag
0063 description: Inverts the PMU interrupt signal.
0064 The PMU is an external Power Management Unit, whose interrupt output
0065 signal is fed into the PMC. This signal is optionally inverted, and
0066 then fed into the ARM GIC. The PMC is not involved in the detection
0067 or handling of this interrupt signal, merely its inversion.
0068
0069 nvidia,core-power-req-active-high:
0070 $ref: /schemas/types.yaml#/definitions/flag
0071 description: Core power request active-high.
0072
0073 nvidia,sys-clock-req-active-high:
0074 $ref: /schemas/types.yaml#/definitions/flag
0075 description: System clock request active-high.
0076
0077 nvidia,combined-power-req:
0078 $ref: /schemas/types.yaml#/definitions/flag
0079 description: combined power request for CPU and Core.
0080
0081 nvidia,cpu-pwr-good-en:
0082 $ref: /schemas/types.yaml#/definitions/flag
0083 description:
0084 CPU power good signal from external PMIC to PMC is enabled.
0085
0086 nvidia,suspend-mode:
0087 $ref: /schemas/types.yaml#/definitions/uint32
0088 enum: [0, 1, 2]
0089 description:
0090 The suspend mode that the platform should use.
0091 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
0092 Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
0093 Mode 2 is for LP2, CPU voltage off
0094
0095 nvidia,cpu-pwr-good-time:
0096 $ref: /schemas/types.yaml#/definitions/uint32
0097 description: CPU power good time in uSec.
0098
0099 nvidia,cpu-pwr-off-time:
0100 $ref: /schemas/types.yaml#/definitions/uint32
0101 description: CPU power off time in uSec.
0102
0103 nvidia,core-pwr-good-time:
0104 $ref: /schemas/types.yaml#/definitions/uint32-array
0105 description:
0106 <Oscillator-stable-time Power-stable-time>
0107 Core power good time in uSec.
0108
0109 nvidia,core-pwr-off-time:
0110 $ref: /schemas/types.yaml#/definitions/uint32
0111 description: Core power off time in uSec.
0112
0113 nvidia,lp0-vec:
0114 $ref: /schemas/types.yaml#/definitions/uint32-array
0115 description:
0116 <start length> Starting address and length of LP0 vector.
0117 The LP0 vector contains the warm boot code that is executed
0118 by AVP when resuming from the LP0 state.
0119 The AVP (Audio-Video Processor) is an ARM7 processor and
0120 always being the first boot processor when chip is power on
0121 or resume from deep sleep mode. When the system is resumed
0122 from the deep sleep mode, the warm boot code will restore
0123 some PLLs, clocks and then brings up CPU0 for resuming the
0124 system.
0125
0126 i2c-thermtrip:
0127 type: object
0128 description:
0129 On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
0130 hardware-triggered thermal reset will be enabled.
0131
0132 properties:
0133 nvidia,i2c-controller-id:
0134 $ref: /schemas/types.yaml#/definitions/uint32
0135 description:
0136 ID of I2C controller to send poweroff command to PMU.
0137 Valid values are described in section 9.2.148
0138 "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
0139 Manual.
0140
0141 nvidia,bus-addr:
0142 $ref: /schemas/types.yaml#/definitions/uint32
0143 description: Bus address of the PMU on the I2C bus.
0144
0145 nvidia,reg-addr:
0146 $ref: /schemas/types.yaml#/definitions/uint32
0147 description: PMU I2C register address to issue poweroff command.
0148
0149 nvidia,reg-data:
0150 $ref: /schemas/types.yaml#/definitions/uint32
0151 description: Poweroff command to write to PMU.
0152
0153 nvidia,pinmux-id:
0154 $ref: /schemas/types.yaml#/definitions/uint32
0155 description:
0156 Pinmux used by the hardware when issuing Poweroff command.
0157 Defaults to 0. Valid values are described in section 12.5.2
0158 "Pinmux Support" of the Tegra4 Technical Reference Manual.
0159
0160 required:
0161 - nvidia,i2c-controller-id
0162 - nvidia,bus-addr
0163 - nvidia,reg-addr
0164 - nvidia,reg-data
0165
0166 additionalProperties: false
0167
0168 powergates:
0169 type: object
0170 description: |
0171 This node contains a hierarchy of power domain nodes, which should
0172 match the powergates on the Tegra SoC. Each powergate node
0173 represents a power-domain on the Tegra SoC that can be power-gated
0174 by the Tegra PMC.
0175 Hardware blocks belonging to a power domain should contain
0176 "power-domains" property that is a phandle pointing to corresponding
0177 powergate node.
0178 The name of the powergate node should be one of the below. Note that
0179 not every powergate is applicable to all Tegra devices and the following
0180 list shows which powergates are applicable to which devices.
0181 Please refer to Tegra TRM for mode details on the powergate nodes to
0182 use for each power-gate block inside Tegra.
0183 Name Description Devices Applicable
0184 3d 3D Graphics Tegra20/114/124/210
0185 3d0 3D Graphics 0 Tegra30
0186 3d1 3D Graphics 1 Tegra30
0187 aud Audio Tegra210
0188 dfd Debug Tegra210
0189 dis Display A Tegra114/124/210
0190 disb Display B Tegra114/124/210
0191 heg 2D Graphics Tegra30/114/124/210
0192 iram Internal RAM Tegra124/210
0193 mpe MPEG Encode All
0194 nvdec NVIDIA Video Decode Engine Tegra210
0195 nvjpg NVIDIA JPEG Engine Tegra210
0196 pcie PCIE Tegra20/30/124/210
0197 sata SATA Tegra30/124/210
0198 sor Display interfaces Tegra124/210
0199 ve2 Video Encode Engine 2 Tegra210
0200 venc Video Encode Engine All
0201 vdec Video Decode Engine Tegra20/30/114/124
0202 vic Video Imaging Compositor Tegra124/210
0203 xusba USB Partition A Tegra114/124/210
0204 xusbb USB Partition B Tegra114/124/210
0205 xusbc USB Partition C Tegra114/124/210
0206
0207 patternProperties:
0208 "^[a-z0-9]+$":
0209 type: object
0210
0211 properties:
0212 clocks:
0213 minItems: 1
0214 maxItems: 8
0215 description:
0216 Must contain an entry for each clock required by the PMC
0217 for controlling a power-gate.
0218 See ../clocks/clock-bindings.txt document for more details.
0219
0220 resets:
0221 minItems: 1
0222 maxItems: 8
0223 description:
0224 Must contain an entry for each reset required by the PMC
0225 for controlling a power-gate.
0226 See ../reset/reset.txt for more details.
0227
0228 '#power-domain-cells':
0229 const: 0
0230 description: Must be 0.
0231
0232 required:
0233 - clocks
0234 - resets
0235 - '#power-domain-cells'
0236
0237 additionalProperties: false
0238
0239 patternProperties:
0240 "^[a-f0-9]+-[a-f0-9]+$":
0241 type: object
0242 description:
0243 This is a Pad configuration node. On Tegra SOCs a pad is a set of
0244 pins which are configured as a group. The pin grouping is a fixed
0245 attribute of the hardware. The PMC can be used to set pad power state
0246 and signaling voltage. A pad can be either in active or power down mode.
0247 The support for power state and signaling voltage configuration varies
0248 depending on the pad in question. 3.3V and 1.8V signaling voltages
0249 are supported on pins where software controllable signaling voltage
0250 switching is available.
0251
0252 The pad configuration state nodes are placed under the pmc node and they
0253 are referred to by the pinctrl client properties. For more information
0254 see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
0255 The pad name should be used as the value of the pins property in pin
0256 configuration nodes.
0257
0258 The following pads are present on Tegra124 and Tegra132
0259 audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
0260 hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
0261 sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
0262
0263 The following pads are present on Tegra210
0264 audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
0265 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
0266 hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
0267 sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
0268
0269 properties:
0270 pins:
0271 $ref: /schemas/types.yaml#/definitions/string
0272 description: Must contain name of the pad(s) to be configured.
0273
0274 low-power-enable:
0275 $ref: /schemas/types.yaml#/definitions/flag
0276 description: Configure the pad into power down mode.
0277
0278 low-power-disable:
0279 $ref: /schemas/types.yaml#/definitions/flag
0280 description: Configure the pad into active mode.
0281
0282 power-source:
0283 $ref: /schemas/types.yaml#/definitions/uint32
0284 description:
0285 Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
0286 TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
0287 The values are defined in
0288 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
0289 Power state can be configured on all Tegra124 and Tegra132
0290 pads. None of the Tegra124 or Tegra132 pads support signaling
0291 voltage switching.
0292 All of the listed Tegra210 pads except pex-cntrl support power
0293 state configuration. Signaling voltage switching is supported
0294 on below Tegra210 pads.
0295 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
0296 sdmmc3, spi, spi-hv, and uart.
0297
0298 required:
0299 - pins
0300
0301 additionalProperties: false
0302
0303 core-domain:
0304 type: object
0305 description: |
0306 The vast majority of hardware blocks of Tegra SoC belong to a
0307 Core power domain, which has a dedicated voltage rail that powers
0308 the blocks.
0309
0310 properties:
0311 operating-points-v2:
0312 description:
0313 Should contain level, voltages and opp-supported-hw property.
0314 The supported-hw is a bitfield indicating SoC speedo or process
0315 ID mask.
0316
0317 "#power-domain-cells":
0318 const: 0
0319
0320 required:
0321 - operating-points-v2
0322 - "#power-domain-cells"
0323
0324 additionalProperties: false
0325
0326 core-supply:
0327 description:
0328 Phandle to voltage regulator connected to the SoC Core power rail.
0329
0330 required:
0331 - compatible
0332 - reg
0333 - clock-names
0334 - clocks
0335 - '#clock-cells'
0336
0337 additionalProperties: false
0338
0339 dependencies:
0340 "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
0341 "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
0342 "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
0343
0344 examples:
0345 - |
0346
0347 #include <dt-bindings/clock/tegra210-car.h>
0348 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
0349 #include <dt-bindings/soc/tegra-pmc.h>
0350
0351 tegra_pmc: pmc@7000e400 {
0352 compatible = "nvidia,tegra210-pmc";
0353 reg = <0x7000e400 0x400>;
0354 core-supply = <®ulator>;
0355 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
0356 clock-names = "pclk", "clk32k_in";
0357 #clock-cells = <1>;
0358
0359 nvidia,invert-interrupt;
0360 nvidia,suspend-mode = <0>;
0361 nvidia,cpu-pwr-good-time = <0>;
0362 nvidia,cpu-pwr-off-time = <0>;
0363 nvidia,core-pwr-good-time = <4587 3876>;
0364 nvidia,core-pwr-off-time = <39065>;
0365 nvidia,core-power-req-active-high;
0366 nvidia,sys-clock-req-active-high;
0367
0368 pd_core: core-domain {
0369 operating-points-v2 = <&core_opp_table>;
0370 #power-domain-cells = <0>;
0371 };
0372
0373 powergates {
0374 pd_audio: aud {
0375 clocks = <&tegra_car TEGRA210_CLK_APE>,
0376 <&tegra_car TEGRA210_CLK_APB2APE>;
0377 resets = <&tegra_car 198>;
0378 power-domains = <&pd_core>;
0379 #power-domain-cells = <0>;
0380 };
0381
0382 pd_xusbss: xusba {
0383 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
0384 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
0385 power-domains = <&pd_core>;
0386 #power-domain-cells = <0>;
0387 };
0388 };
0389 };
