0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: NVIDIA Tegra194 CBB 1.0 bindings
0008
0009 maintainers:
0010 - Sumit Gupta <sumitg@nvidia.com>
0011
0012 description: |+
0013 The Control Backbone (CBB) is comprised of the physical path from an
0014 initiator to a target's register configuration space. CBB 1.0 has
0015 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
0016 initiators and targets using different bridges like AXIP2P, AXI2APB.
0017
0018 This driver handles errors due to illegal register accesses reported
0019 by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs
0020 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
0021 which is the main NOC.
0022
0023 By default, the access issuing initiator is informed about the error
0024 using SError or Data Abort exception unless the ERD (Error Response
0025 Disable) is enabled/set for that initiator. If the ERD is enabled, then
0026 SError or Data Abort is masked and the error is reported with interrupt.
0027
0028 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
0029 errors due to illegal accesses from CCPLEX are reported by interrupts.
0030 If ERD is not set, then error is reported by SError.
0031 - For other initiators, the ERD is disabled. So, the access issuing
0032 initiator is informed about the illegal access by Data Abort exception.
0033 In addition, an interrupt is also generated to CCPLEX. These initiators
0034 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
0035 engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder
0036 engine) etc which can initiate transactions.
0037
0038 The driver prints relevant debug information like Error Code, Error
0039 Description, Master, Address, AXI ID, Cache, Protection, Security Group
0040 etc on receiving error notification.
0041
0042 properties:
0043 $nodename:
0044 pattern: "^[a-z]+-noc@[0-9a-f]+$"
0045
0046 compatible:
0047 enum:
0048 - nvidia,tegra194-cbb-noc
0049 - nvidia,tegra194-aon-noc
0050 - nvidia,tegra194-bpmp-noc
0051 - nvidia,tegra194-rce-noc
0052 - nvidia,tegra194-sce-noc
0053
0054 reg:
0055 maxItems: 1
0056
0057 interrupts:
0058 description:
0059 CCPLEX receives secure or nonsecure interrupt depending on error type.
0060 A secure interrupt is received for SEC(firewall) & SLV errors and a
0061 non-secure interrupt is received for TMO & DEC errors.
0062 items:
0063 - description: non-secure interrupt
0064 - description: secure interrupt
0065
0066 nvidia,axi2apb:
0067 $ref: '/schemas/types.yaml#/definitions/phandle'
0068 description:
0069 Specifies the node having all axi2apb bridges which need to be checked
0070 for any error logged in their status register.
0071
0072 nvidia,apbmisc:
0073 $ref: '/schemas/types.yaml#/definitions/phandle'
0074 description:
0075 Specifies the apbmisc node which need to be used for reading the ERD
0076 register.
0077
0078 additionalProperties: false
0079
0080 required:
0081 - compatible
0082 - reg
0083 - interrupts
0084 - nvidia,apbmisc
0085
0086 examples:
0087 - |
0088 #include <dt-bindings/interrupt-controller/arm-gic.h>
0089
0090 cbb-noc@2300000 {
0091 compatible = "nvidia,tegra194-cbb-noc";
0092 reg = <0x02300000 0x1000>;
0093 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
0094 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
0095 nvidia,axi2apb = <&axi2apb>;
0096 nvidia,apbmisc = <&apbmisc>;
0097 };
