0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra Power Management Controller (PMC)
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014 compatible:
0015 enum:
0016 - nvidia,tegra186-pmc
0017 - nvidia,tegra194-pmc
0018 - nvidia,tegra234-pmc
0019
0020 reg:
0021 minItems: 4
0022 maxItems: 5
0023
0024 reg-names:
0025 minItems: 4
0026 items:
0027 - const: pmc
0028 - const: wake
0029 - const: aotag
0030 - const: scratch
0031 - const: misc
0032
0033 interrupt-controller: true
0034
0035 "#interrupt-cells":
0036 description: Specifies the number of cells needed to encode an
0037 interrupt source. The value must be 2.
0038 const: 2
0039
0040 nvidia,invert-interrupt:
0041 description: If present, inverts the PMU interrupt signal.
0042 $ref: /schemas/types.yaml#/definitions/flag
0043
0044 if:
0045 properties:
0046 compatible:
0047 contains:
0048 const: nvidia,tegra186-pmc
0049 then:
0050 properties:
0051 reg:
0052 maxItems: 4
0053
0054 reg-names:
0055 maxItems: 4
0056 else:
0057 properties:
0058 reg:
0059 minItems: 5
0060
0061 reg-names:
0062 minItems: 5
0063
0064 patternProperties:
0065 "^[a-z0-9]+-[a-z0-9]+$":
0066 if:
0067 type: object
0068 then:
0069 description: |
0070 These are pad configuration nodes. On Tegra SoCs a pad is a set of
0071 pins which are configured as a group. The pin grouping is a fixed
0072 attribute of the hardware. The PMC can be used to set pad power
0073 state and signaling voltage. A pad can be either in active or
0074 power down mode. The support for power state and signaling voltage
0075 configuration varies depending on the pad in question. 3.3 V and
0076 1.8 V signaling voltages are supported on pins where software
0077 controllable signaling voltage switching is available.
0078
0079 Pad configurations are described with pin configuration nodes
0080 which are placed under the pmc node and they are referred to by
0081 the pinctrl client properties. For more information see
0082
0083 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
0084
0085 The following pads are present on Tegra186:
0086
0087 csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
0088 pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
0089 hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
0090 dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
0091 sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
0092
0093 The following pads are present on Tegra194:
0094
0095 csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
0096 pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
0097 pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
0098 soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
0099 hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
0100 pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
0101 spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
0102 audio-hv, ao-hv
0103
0104 properties:
0105 pins:
0106 $ref: /schemas/types.yaml#/definitions/string
0107 description: Must contain the name of the pad(s) to be
0108 configured.
0109
0110 low-power-enable:
0111 description: Configure the pad into power down mode.
0112 $ref: /schemas/types.yaml#/definitions/flag
0113
0114 low-power-disable:
0115 description: Configure the pad into active mode.
0116 $ref: /schemas/types.yaml#/definitions/flag
0117
0118 power-source:
0119 $ref: /schemas/types.yaml#/definitions/uint32
0120 description: |
0121 Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
0122 TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
0123 voltages.
0124
0125 The values are defined in
0126
0127 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
0128
0129 The power state can be configured on all of the above pads
0130 except for ao-hv. Following pads have software configurable
0131 signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
0132 audio-hv, ao-hv.
0133
0134 phandle: true
0135
0136 required:
0137 - pins
0138
0139 additionalProperties: false
0140
0141 required:
0142 - compatible
0143 - reg
0144 - reg-names
0145
0146 additionalProperties: false
0147
0148 dependencies:
0149 interrupt-controller: ['#interrupt-cells']
0150 "#interrupt-cells":
0151 required:
0152 - interrupt-controller
0153
0154 examples:
0155 - |
0156 #include <dt-bindings/clock/tegra186-clock.h>
0157 #include <dt-bindings/interrupt-controller/arm-gic.h>
0158 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
0159 #include <dt-bindings/memory/tegra186-mc.h>
0160 #include <dt-bindings/reset/tegra186-reset.h>
0161
0162 pmc@c3600000 {
0163 compatible = "nvidia,tegra186-pmc";
0164 reg = <0x0c360000 0x10000>,
0165 <0x0c370000 0x10000>,
0166 <0x0c380000 0x10000>,
0167 <0x0c390000 0x10000>;
0168 reg-names = "pmc", "wake", "aotag", "scratch";
0169 nvidia,invert-interrupt;
0170
0171 sdmmc1_3v3: sdmmc1-3v3 {
0172 pins = "sdmmc1-hv";
0173 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
0174 };
0175
0176 sdmmc1_1v8: sdmmc1-1v8 {
0177 pins = "sdmmc1-hv";
0178 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
0179 };
0180 };
0181
0182 sdmmc1: mmc@3400000 {
0183 compatible = "nvidia,tegra186-sdhci";
0184 reg = <0x03400000 0x10000>;
0185 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0186 clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
0187 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
0188 clock-names = "sdhci", "tmclk";
0189 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
0190 reset-names = "sdhci";
0191 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
0192 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
0193 interconnect-names = "dma-mem", "write";
0194 iommus = <&smmu TEGRA186_SID_SDMMC1>;
0195 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
0196 pinctrl-0 = <&sdmmc1_3v3>;
0197 pinctrl-1 = <&sdmmc1_1v8>;
0198 };
