0001 Synaptics SoC Device Tree Bindings
0002
0003 According to https://www.synaptics.com/company/news/conexant-marvell
0004 Synaptics has acquired the Multimedia Solutions Business of Marvell, so
0005 berlin SoCs are now Synaptics' SoCs now.
0006
0007 ---------------------------------------------------------------
0008
0009 Work in progress statement:
0010
0011 Device tree files and bindings applying to Marvell Berlin SoCs and boards are
0012 considered "unstable". Any Marvell Berlin device tree binding may change at any
0013 time. Be sure to use a device tree binary and a kernel image generated from the
0014 same source tree.
0015
0016 Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
0017 stable binding/ABI.
0018
0019 ---------------------------------------------------------------
0020
0021 Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
0022 shall have the following properties:
0023
0024 * Required root node properties:
0025 compatible: must contain "marvell,berlin"
0026
0027 In addition, the above compatible shall be extended with the specific
0028 SoC and board used. Currently known SoC compatibles are:
0029 "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
0030 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
0031 "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
0032 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
0033 "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
0034
0035 * Example:
0036
0037 / {
0038 model = "Sony NSZ-GS7";
0039 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
0040
0041 ...
0042 }
0043
0044 * Marvell Berlin CPU control bindings
0045
0046 CPU control register allows various operations on CPUs, like resetting them
0047 independently.
0048
0049 Required properties:
0050 - compatible: should be "marvell,berlin-cpu-ctrl"
0051 - reg: address and length of the register set
0052
0053 Example:
0054
0055 cpu-ctrl@f7dd0000 {
0056 compatible = "marvell,berlin-cpu-ctrl";
0057 reg = <0xf7dd0000 0x10000>;
0058 };
0059
0060 * Marvell Berlin2 chip control binding
0061
0062 Marvell Berlin SoCs have a chip control register set providing several
0063 individual registers dealing with pinmux, padmux, clock, reset, and secondary
0064 CPU boot address. Unfortunately, the individual registers are spread among the
0065 chip control registers, so there should be a single DT node only providing the
0066 different functions which are described below.
0067
0068 Required properties:
0069 - compatible:
0070 * the first and second values must be:
0071 "simple-mfd", "syscon"
0072 - reg: address and length of following register sets for
0073 BG2/BG2CD: chip control register set
0074 BG2Q: chip control register set and cpu pll registers
0075
0076 * Marvell Berlin2 system control binding
0077
0078 Marvell Berlin SoCs have a system control register set providing several
0079 individual registers dealing with pinmux, padmux, and reset.
0080
0081 Required properties:
0082 - compatible:
0083 * the first and second values must be:
0084 "simple-mfd", "syscon"
0085 - reg: address and length of the system control register set
0086
0087 Example:
0088
0089 chip: chip-control@ea0000 {
0090 compatible = "simple-mfd", "syscon";
0091 reg = <0xea0000 0x400>;
0092
0093 /* sub-device nodes */
0094 };
0095
0096 sysctrl: system-controller@d000 {
0097 compatible = "simple-mfd", "syscon";
0098 reg = <0xd000 0x100>;
0099
0100 /* sub-device nodes */
0101 };
