0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/pmu.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM Performance Monitor Units
0008
0009 maintainers:
0010 - Mark Rutland <mark.rutland@arm.com>
0011 - Will Deacon <will.deacon@arm.com>
0012
0013 description: |+
0014 ARM cores often have a PMU for counting cpu and cache events like cache misses
0015 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
0016 representation in the device tree should be done as under:-
0017
0018 properties:
0019 compatible:
0020 items:
0021 - enum:
0022 - apm,potenza-pmu
0023 - apple,firestorm-pmu
0024 - apple,icestorm-pmu
0025 - arm,armv8-pmuv3 # Only for s/w models
0026 - arm,arm1136-pmu
0027 - arm,arm1176-pmu
0028 - arm,arm11mpcore-pmu
0029 - arm,cortex-a5-pmu
0030 - arm,cortex-a7-pmu
0031 - arm,cortex-a8-pmu
0032 - arm,cortex-a9-pmu
0033 - arm,cortex-a12-pmu
0034 - arm,cortex-a15-pmu
0035 - arm,cortex-a17-pmu
0036 - arm,cortex-a32-pmu
0037 - arm,cortex-a34-pmu
0038 - arm,cortex-a35-pmu
0039 - arm,cortex-a53-pmu
0040 - arm,cortex-a55-pmu
0041 - arm,cortex-a57-pmu
0042 - arm,cortex-a65-pmu
0043 - arm,cortex-a72-pmu
0044 - arm,cortex-a73-pmu
0045 - arm,cortex-a75-pmu
0046 - arm,cortex-a76-pmu
0047 - arm,cortex-a77-pmu
0048 - arm,cortex-a78-pmu
0049 - arm,cortex-a510-pmu
0050 - arm,cortex-a710-pmu
0051 - arm,cortex-x1-pmu
0052 - arm,cortex-x2-pmu
0053 - arm,neoverse-e1-pmu
0054 - arm,neoverse-n1-pmu
0055 - arm,neoverse-n2-pmu
0056 - arm,neoverse-v1-pmu
0057 - brcm,vulcan-pmu
0058 - cavium,thunder-pmu
0059 - nvidia,denver-pmu
0060 - nvidia,carmel-pmu
0061 - qcom,krait-pmu
0062 - qcom,scorpion-pmu
0063 - qcom,scorpion-mp-pmu
0064
0065 interrupts:
0066 # Don't know how many CPUs, so no constraints to specify
0067 description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
0068
0069 interrupt-affinity:
0070 $ref: /schemas/types.yaml#/definitions/phandle-array
0071 items:
0072 maxItems: 1
0073 description:
0074 When using SPIs, specifies a list of phandles to CPU
0075 nodes corresponding directly to the affinity of
0076 the SPIs listed in the interrupts property.
0077
0078 When using a PPI, specifies a list of phandles to CPU
0079 nodes corresponding to the set of CPUs which have
0080 a PMU of this type signalling the PPI listed in the
0081 interrupts property, unless this is already specified
0082 by the PPI interrupt specifier itself (in which case
0083 the interrupt-affinity property shouldn't be present).
0084
0085 This property should be present when there is more than
0086 a single SPI.
0087
0088 qcom,no-pc-write:
0089 type: boolean
0090 description:
0091 Indicates that this PMU doesn't support the 0xc and 0xd events.
0092
0093 secure-reg-access:
0094 type: boolean
0095 description:
0096 Indicates that the ARMv7 Secure Debug Enable Register
0097 (SDER) is accessible. This will cause the driver to do
0098 any setup required that is only possible in ARMv7 secure
0099 state. If not present the ARMv7 SDER will not be touched,
0100 which means the PMU may fail to operate unless external
0101 code (bootloader or security monitor) has performed the
0102 appropriate initialisation. Note that this property is
0103 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
0104 in Non-secure state.
0105
0106 required:
0107 - compatible
0108
0109 additionalProperties: false
0110
0111 ...
