0001 Some socs have a large number of interrupts requests to service
0002 the needs of its many peripherals and subsystems. All of the
0003 interrupt lines from the subsystems are not needed at the same
0004 time, so they have to be muxed to the irq-controller appropriately.
0005 In such places a interrupt controllers are preceded by an CROSSBAR
0006 that provides flexibility in muxing the device requests to the controller
0007 inputs.
0008
0009 Required properties:
0010 - compatible : Should be "ti,irq-crossbar"
0011 - reg: Base address and the size of the crossbar registers.
0012 - interrupt-controller: indicates that this block is an interrupt controller.
0013 - ti,max-irqs: Total number of irqs available at the parent interrupt controller.
0014 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
0015 - ti,reg-size: Size of a individual register in bytes. Every individual
0016 register is assumed to be of same size. Valid sizes are 1, 2, 4.
0017 - ti,irqs-reserved: List of the reserved irq lines that are not muxed using
0018 crossbar. These interrupt lines are reserved in the soc,
0019 so crossbar bar driver should not consider them as free
0020 lines.
0021
0022 Optional properties:
0023 - ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
0024 SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
0025 crossbar. These irqs have a crossbar register, but still cannot be used.
0026
0027 - ti,irqs-safe-map: integer which maps to a safe configuration to use
0028 when the interrupt controller irq is unused (when not provided, default is 0)
0029
0030 Examples:
0031 crossbar_mpu: crossbar@4a002a48 {
0032 compatible = "ti,irq-crossbar";
0033 reg = <0x4a002a48 0x130>;
0034 ti,max-irqs = <160>;
0035 ti,max-crossbar-sources = <400>;
0036 ti,reg-size = <2>;
0037 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
0038 ti,irqs-skip = <10 133 139 140>;
0039 };
0040
0041 Consumer:
0042 ========
0043 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
0044 Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for
0045 further details.
0046
0047 An interrupt consumer on an SoC using crossbar will use:
0048 interrupts = <GIC_SPI request_number interrupt_level>
0049
0050 Example:
0051 device_x@4a023000 {
0052 /* Crossbar 8 used */
0053 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0054 ...
0055 };
