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OSCL-LXR

 
 

    


0001 Mediatek vcodecsys controller
0002 ============================
0003 
0004 The Mediatek vcodecsys controller provides various clocks to the system.
0005 
0006 Required Properties:
0007 
0008 - compatible: Should be one of:
0009         - "mediatek,mt6765-vcodecsys", "syscon"
0010 - #clock-cells: Must be 1
0011 
0012 The vcodecsys controller uses the common clk binding from
0013 Documentation/devicetree/bindings/clock/clock-bindings.txt
0014 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
0015 
0016 The vcodecsys controller also uses the common power domain from
0017 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
0018 The available power doamins are defined in dt-bindings/power/mt*-power.h.
0019 
0020 Example:
0021 
0022 venc_gcon: clock-controller@17000000 {
0023         compatible = "mediatek,mt6765-vcodecsys", "syscon";
0024         reg = <0 0x17000000 0 0x10000>;
0025         power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>;
0026         #clock-cells = <1>;
0027 };