0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: MediaTek System Clock Controller for MT8195
0008
0009 maintainers:
0010 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
0011
0012 description:
0013 The clock architecture in Mediatek like below
0014 PLLs -->
0015 dividers -->
0016 muxes
0017 -->
0018 clock gate
0019
0020 The apmixedsys provides most of PLLs which generated from SoC 26m.
0021 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
0022 The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
0023
0024 properties:
0025 compatible:
0026 items:
0027 - enum:
0028 - mediatek,mt8195-topckgen
0029 - mediatek,mt8195-infracfg_ao
0030 - mediatek,mt8195-apmixedsys
0031 - mediatek,mt8195-pericfg_ao
0032 - const: syscon
0033
0034 reg:
0035 maxItems: 1
0036
0037 '#clock-cells':
0038 const: 1
0039
0040 '#reset-cells':
0041 const: 1
0042
0043 required:
0044 - compatible
0045 - reg
0046
0047 additionalProperties: false
0048
0049 examples:
0050 - |
0051 topckgen: syscon@10000000 {
0052 compatible = "mediatek,mt8195-topckgen", "syscon";
0053 reg = <0x10000000 0x1000>;
0054 #clock-cells = <1>;
0055 };
0056
0057 - |
0058 infracfg_ao: syscon@10001000 {
0059 compatible = "mediatek,mt8195-infracfg_ao", "syscon";
0060 reg = <0x10001000 0x1000>;
0061 #clock-cells = <1>;
0062 };
0063
0064 - |
0065 apmixedsys: syscon@1000c000 {
0066 compatible = "mediatek,mt8195-apmixedsys", "syscon";
0067 reg = <0x1000c000 0x1000>;
0068 #clock-cells = <1>;
0069 };
0070
0071 - |
0072 pericfg_ao: syscon@11003000 {
0073 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
0074 reg = <0x11003000 0x1000>;
0075 #clock-cells = <1>;
0076 };
