0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: MediaTek Functional Clock Controller for MT8195
0008
0009 maintainers:
0010 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
0011
0012 description:
0013 The clock architecture in Mediatek like below
0014 PLLs -->
0015 dividers -->
0016 muxes
0017 -->
0018 clock gate
0019
0020 The devices except apusys_pll provide clock gate control in different IP blocks.
0021 The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
0022
0023 properties:
0024 compatible:
0025 items:
0026 - enum:
0027 - mediatek,mt8195-scp_adsp
0028 - mediatek,mt8195-imp_iic_wrap_s
0029 - mediatek,mt8195-imp_iic_wrap_w
0030 - mediatek,mt8195-mfgcfg
0031 - mediatek,mt8195-vppsys0
0032 - mediatek,mt8195-wpesys
0033 - mediatek,mt8195-wpesys_vpp0
0034 - mediatek,mt8195-wpesys_vpp1
0035 - mediatek,mt8195-vppsys1
0036 - mediatek,mt8195-imgsys
0037 - mediatek,mt8195-imgsys1_dip_top
0038 - mediatek,mt8195-imgsys1_dip_nr
0039 - mediatek,mt8195-imgsys1_wpe
0040 - mediatek,mt8195-ipesys
0041 - mediatek,mt8195-camsys
0042 - mediatek,mt8195-camsys_rawa
0043 - mediatek,mt8195-camsys_yuva
0044 - mediatek,mt8195-camsys_rawb
0045 - mediatek,mt8195-camsys_yuvb
0046 - mediatek,mt8195-camsys_mraw
0047 - mediatek,mt8195-ccusys
0048 - mediatek,mt8195-vdecsys_soc
0049 - mediatek,mt8195-vdecsys
0050 - mediatek,mt8195-vdecsys_core1
0051 - mediatek,mt8195-vencsys
0052 - mediatek,mt8195-vencsys_core1
0053 - mediatek,mt8195-apusys_pll
0054 reg:
0055 maxItems: 1
0056
0057 '#clock-cells':
0058 const: 1
0059
0060 required:
0061 - compatible
0062 - reg
0063
0064 additionalProperties: false
0065
0066 examples:
0067 - |
0068 scp_adsp: clock-controller@10720000 {
0069 compatible = "mediatek,mt8195-scp_adsp";
0070 reg = <0x10720000 0x1000>;
0071 #clock-cells = <1>;
0072 };
0073
0074 - |
0075 imp_iic_wrap_s: clock-controller@11d03000 {
0076 compatible = "mediatek,mt8195-imp_iic_wrap_s";
0077 reg = <0x11d03000 0x1000>;
0078 #clock-cells = <1>;
0079 };
0080
0081 - |
0082 imp_iic_wrap_w: clock-controller@11e05000 {
0083 compatible = "mediatek,mt8195-imp_iic_wrap_w";
0084 reg = <0x11e05000 0x1000>;
0085 #clock-cells = <1>;
0086 };
0087
0088 - |
0089 mfgcfg: clock-controller@13fbf000 {
0090 compatible = "mediatek,mt8195-mfgcfg";
0091 reg = <0x13fbf000 0x1000>;
0092 #clock-cells = <1>;
0093 };
0094
0095 - |
0096 vppsys0: clock-controller@14000000 {
0097 compatible = "mediatek,mt8195-vppsys0";
0098 reg = <0x14000000 0x1000>;
0099 #clock-cells = <1>;
0100 };
0101
0102 - |
0103 wpesys: clock-controller@14e00000 {
0104 compatible = "mediatek,mt8195-wpesys";
0105 reg = <0x14e00000 0x1000>;
0106 #clock-cells = <1>;
0107 };
0108
0109 - |
0110 wpesys_vpp0: clock-controller@14e02000 {
0111 compatible = "mediatek,mt8195-wpesys_vpp0";
0112 reg = <0x14e02000 0x1000>;
0113 #clock-cells = <1>;
0114 };
0115
0116 - |
0117 wpesys_vpp1: clock-controller@14e03000 {
0118 compatible = "mediatek,mt8195-wpesys_vpp1";
0119 reg = <0x14e03000 0x1000>;
0120 #clock-cells = <1>;
0121 };
0122
0123 - |
0124 vppsys1: clock-controller@14f00000 {
0125 compatible = "mediatek,mt8195-vppsys1";
0126 reg = <0x14f00000 0x1000>;
0127 #clock-cells = <1>;
0128 };
0129
0130 - |
0131 imgsys: clock-controller@15000000 {
0132 compatible = "mediatek,mt8195-imgsys";
0133 reg = <0x15000000 0x1000>;
0134 #clock-cells = <1>;
0135 };
0136
0137 - |
0138 imgsys1_dip_top: clock-controller@15110000 {
0139 compatible = "mediatek,mt8195-imgsys1_dip_top";
0140 reg = <0x15110000 0x1000>;
0141 #clock-cells = <1>;
0142 };
0143
0144 - |
0145 imgsys1_dip_nr: clock-controller@15130000 {
0146 compatible = "mediatek,mt8195-imgsys1_dip_nr";
0147 reg = <0x15130000 0x1000>;
0148 #clock-cells = <1>;
0149 };
0150
0151 - |
0152 imgsys1_wpe: clock-controller@15220000 {
0153 compatible = "mediatek,mt8195-imgsys1_wpe";
0154 reg = <0x15220000 0x1000>;
0155 #clock-cells = <1>;
0156 };
0157
0158 - |
0159 ipesys: clock-controller@15330000 {
0160 compatible = "mediatek,mt8195-ipesys";
0161 reg = <0x15330000 0x1000>;
0162 #clock-cells = <1>;
0163 };
0164
0165 - |
0166 camsys: clock-controller@16000000 {
0167 compatible = "mediatek,mt8195-camsys";
0168 reg = <0x16000000 0x1000>;
0169 #clock-cells = <1>;
0170 };
0171
0172 - |
0173 camsys_rawa: clock-controller@1604f000 {
0174 compatible = "mediatek,mt8195-camsys_rawa";
0175 reg = <0x1604f000 0x1000>;
0176 #clock-cells = <1>;
0177 };
0178
0179 - |
0180 camsys_yuva: clock-controller@1606f000 {
0181 compatible = "mediatek,mt8195-camsys_yuva";
0182 reg = <0x1606f000 0x1000>;
0183 #clock-cells = <1>;
0184 };
0185
0186 - |
0187 camsys_rawb: clock-controller@1608f000 {
0188 compatible = "mediatek,mt8195-camsys_rawb";
0189 reg = <0x1608f000 0x1000>;
0190 #clock-cells = <1>;
0191 };
0192
0193 - |
0194 camsys_yuvb: clock-controller@160af000 {
0195 compatible = "mediatek,mt8195-camsys_yuvb";
0196 reg = <0x160af000 0x1000>;
0197 #clock-cells = <1>;
0198 };
0199
0200 - |
0201 camsys_mraw: clock-controller@16140000 {
0202 compatible = "mediatek,mt8195-camsys_mraw";
0203 reg = <0x16140000 0x1000>;
0204 #clock-cells = <1>;
0205 };
0206
0207 - |
0208 ccusys: clock-controller@17200000 {
0209 compatible = "mediatek,mt8195-ccusys";
0210 reg = <0x17200000 0x1000>;
0211 #clock-cells = <1>;
0212 };
0213
0214 - |
0215 vdecsys_soc: clock-controller@1800f000 {
0216 compatible = "mediatek,mt8195-vdecsys_soc";
0217 reg = <0x1800f000 0x1000>;
0218 #clock-cells = <1>;
0219 };
0220
0221 - |
0222 vdecsys: clock-controller@1802f000 {
0223 compatible = "mediatek,mt8195-vdecsys";
0224 reg = <0x1802f000 0x1000>;
0225 #clock-cells = <1>;
0226 };
0227
0228 - |
0229 vdecsys_core1: clock-controller@1803f000 {
0230 compatible = "mediatek,mt8195-vdecsys_core1";
0231 reg = <0x1803f000 0x1000>;
0232 #clock-cells = <1>;
0233 };
0234
0235 - |
0236 vencsys: clock-controller@1a000000 {
0237 compatible = "mediatek,mt8195-vencsys";
0238 reg = <0x1a000000 0x1000>;
0239 #clock-cells = <1>;
0240 };
0241
0242 - |
0243 vencsys_core1: clock-controller@1b000000 {
0244 compatible = "mediatek,mt8195-vencsys_core1";
0245 reg = <0x1b000000 0x1000>;
0246 #clock-cells = <1>;
0247 };
0248
0249 - |
0250 apusys_pll: clock-controller@190f3000 {
0251 compatible = "mediatek,mt8195-apusys_pll";
0252 reg = <0x190f3000 0x1000>;
0253 #clock-cells = <1>;
0254 };
