0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: MediaTek System Clock Controller for MT8192
0008
0009 maintainers:
0010 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
0011
0012 description:
0013 The Mediatek system clock controller provides various clocks and system configuration
0014 like reset and bus protection on MT8192.
0015
0016 properties:
0017 compatible:
0018 items:
0019 - enum:
0020 - mediatek,mt8192-topckgen
0021 - mediatek,mt8192-infracfg
0022 - mediatek,mt8192-pericfg
0023 - mediatek,mt8192-apmixedsys
0024 - const: syscon
0025
0026 reg:
0027 maxItems: 1
0028
0029 '#clock-cells':
0030 const: 1
0031
0032 '#reset-cells':
0033 const: 1
0034
0035 required:
0036 - compatible
0037 - reg
0038
0039 additionalProperties: false
0040
0041 examples:
0042 - |
0043 topckgen: syscon@10000000 {
0044 compatible = "mediatek,mt8192-topckgen", "syscon";
0045 reg = <0x10000000 0x1000>;
0046 #clock-cells = <1>;
0047 };
0048
0049 - |
0050 infracfg: syscon@10001000 {
0051 compatible = "mediatek,mt8192-infracfg", "syscon";
0052 reg = <0x10001000 0x1000>;
0053 #clock-cells = <1>;
0054 };
0055
0056 - |
0057 pericfg: syscon@10003000 {
0058 compatible = "mediatek,mt8192-pericfg", "syscon";
0059 reg = <0x10003000 0x1000>;
0060 #clock-cells = <1>;
0061 };
0062
0063 - |
0064 apmixedsys: syscon@1000c000 {
0065 compatible = "mediatek,mt8192-apmixedsys", "syscon";
0066 reg = <0x1000c000 0x1000>;
0067 #clock-cells = <1>;
0068 };
