0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: MediaTek Functional Clock Controller for MT8192
0008
0009 maintainers:
0010 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
0011
0012 description:
0013 The Mediatek functional clock controller provides various clocks on MT8192.
0014
0015 properties:
0016 compatible:
0017 items:
0018 - enum:
0019 - mediatek,mt8192-scp_adsp
0020 - mediatek,mt8192-imp_iic_wrap_c
0021 - mediatek,mt8192-imp_iic_wrap_e
0022 - mediatek,mt8192-imp_iic_wrap_s
0023 - mediatek,mt8192-imp_iic_wrap_ws
0024 - mediatek,mt8192-imp_iic_wrap_w
0025 - mediatek,mt8192-imp_iic_wrap_n
0026 - mediatek,mt8192-msdc_top
0027 - mediatek,mt8192-mfgcfg
0028 - mediatek,mt8192-imgsys
0029 - mediatek,mt8192-imgsys2
0030 - mediatek,mt8192-vdecsys_soc
0031 - mediatek,mt8192-vdecsys
0032 - mediatek,mt8192-vencsys
0033 - mediatek,mt8192-camsys
0034 - mediatek,mt8192-camsys_rawa
0035 - mediatek,mt8192-camsys_rawb
0036 - mediatek,mt8192-camsys_rawc
0037 - mediatek,mt8192-ipesys
0038 - mediatek,mt8192-mdpsys
0039
0040 reg:
0041 maxItems: 1
0042
0043 '#clock-cells':
0044 const: 1
0045
0046 required:
0047 - compatible
0048 - reg
0049
0050 additionalProperties: false
0051
0052 examples:
0053 - |
0054 scp_adsp: clock-controller@10720000 {
0055 compatible = "mediatek,mt8192-scp_adsp";
0056 reg = <0x10720000 0x1000>;
0057 #clock-cells = <1>;
0058 };
0059
0060 - |
0061 imp_iic_wrap_c: clock-controller@11007000 {
0062 compatible = "mediatek,mt8192-imp_iic_wrap_c";
0063 reg = <0x11007000 0x1000>;
0064 #clock-cells = <1>;
0065 };
0066
0067 - |
0068 imp_iic_wrap_e: clock-controller@11cb1000 {
0069 compatible = "mediatek,mt8192-imp_iic_wrap_e";
0070 reg = <0x11cb1000 0x1000>;
0071 #clock-cells = <1>;
0072 };
0073
0074 - |
0075 imp_iic_wrap_s: clock-controller@11d03000 {
0076 compatible = "mediatek,mt8192-imp_iic_wrap_s";
0077 reg = <0x11d03000 0x1000>;
0078 #clock-cells = <1>;
0079 };
0080
0081 - |
0082 imp_iic_wrap_ws: clock-controller@11d23000 {
0083 compatible = "mediatek,mt8192-imp_iic_wrap_ws";
0084 reg = <0x11d23000 0x1000>;
0085 #clock-cells = <1>;
0086 };
0087
0088 - |
0089 imp_iic_wrap_w: clock-controller@11e01000 {
0090 compatible = "mediatek,mt8192-imp_iic_wrap_w";
0091 reg = <0x11e01000 0x1000>;
0092 #clock-cells = <1>;
0093 };
0094
0095 - |
0096 imp_iic_wrap_n: clock-controller@11f02000 {
0097 compatible = "mediatek,mt8192-imp_iic_wrap_n";
0098 reg = <0x11f02000 0x1000>;
0099 #clock-cells = <1>;
0100 };
0101
0102 - |
0103 msdc_top: clock-controller@11f10000 {
0104 compatible = "mediatek,mt8192-msdc_top";
0105 reg = <0x11f10000 0x1000>;
0106 #clock-cells = <1>;
0107 };
0108
0109 - |
0110 mfgcfg: clock-controller@13fbf000 {
0111 compatible = "mediatek,mt8192-mfgcfg";
0112 reg = <0x13fbf000 0x1000>;
0113 #clock-cells = <1>;
0114 };
0115
0116 - |
0117 imgsys: clock-controller@15020000 {
0118 compatible = "mediatek,mt8192-imgsys";
0119 reg = <0x15020000 0x1000>;
0120 #clock-cells = <1>;
0121 };
0122
0123 - |
0124 imgsys2: clock-controller@15820000 {
0125 compatible = "mediatek,mt8192-imgsys2";
0126 reg = <0x15820000 0x1000>;
0127 #clock-cells = <1>;
0128 };
0129
0130 - |
0131 vdecsys_soc: clock-controller@1600f000 {
0132 compatible = "mediatek,mt8192-vdecsys_soc";
0133 reg = <0x1600f000 0x1000>;
0134 #clock-cells = <1>;
0135 };
0136
0137 - |
0138 vdecsys: clock-controller@1602f000 {
0139 compatible = "mediatek,mt8192-vdecsys";
0140 reg = <0x1602f000 0x1000>;
0141 #clock-cells = <1>;
0142 };
0143
0144 - |
0145 vencsys: clock-controller@17000000 {
0146 compatible = "mediatek,mt8192-vencsys";
0147 reg = <0x17000000 0x1000>;
0148 #clock-cells = <1>;
0149 };
0150
0151 - |
0152 camsys: clock-controller@1a000000 {
0153 compatible = "mediatek,mt8192-camsys";
0154 reg = <0x1a000000 0x1000>;
0155 #clock-cells = <1>;
0156 };
0157
0158 - |
0159 camsys_rawa: clock-controller@1a04f000 {
0160 compatible = "mediatek,mt8192-camsys_rawa";
0161 reg = <0x1a04f000 0x1000>;
0162 #clock-cells = <1>;
0163 };
0164
0165 - |
0166 camsys_rawb: clock-controller@1a06f000 {
0167 compatible = "mediatek,mt8192-camsys_rawb";
0168 reg = <0x1a06f000 0x1000>;
0169 #clock-cells = <1>;
0170 };
0171
0172 - |
0173 camsys_rawc: clock-controller@1a08f000 {
0174 compatible = "mediatek,mt8192-camsys_rawc";
0175 reg = <0x1a08f000 0x1000>;
0176 #clock-cells = <1>;
0177 };
0178
0179 - |
0180 ipesys: clock-controller@1b000000 {
0181 compatible = "mediatek,mt8192-ipesys";
0182 reg = <0x1b000000 0x1000>;
0183 #clock-cells = <1>;
0184 };
0185
0186 - |
0187 mdpsys: clock-controller@1f000000 {
0188 compatible = "mediatek,mt8192-mdpsys";
0189 reg = <0x1f000000 0x1000>;
0190 #clock-cells = <1>;
0191 };
