0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: MediaTek System Clock Controller for MT8186
0008
0009 maintainers:
0010 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
0011
0012 description: |
0013 The clock architecture in MediaTek like below
0014 PLLs -->
0015 dividers -->
0016 muxes
0017 -->
0018 clock gate
0019
0020 The apmixedsys provides most of PLLs which generated from SoC 26m.
0021 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
0022 The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
0023 The mcusys provides mux control to select the clock source in AP MCU.
0024 The device nodes also provide the system control capacity for configuration.
0025
0026 properties:
0027 compatible:
0028 items:
0029 - enum:
0030 - mediatek,mt8186-mcusys
0031 - mediatek,mt8186-topckgen
0032 - mediatek,mt8186-infracfg_ao
0033 - mediatek,mt8186-apmixedsys
0034 - const: syscon
0035
0036 reg:
0037 maxItems: 1
0038
0039 '#clock-cells':
0040 const: 1
0041
0042 '#reset-cells':
0043 const: 1
0044
0045 required:
0046 - compatible
0047 - reg
0048
0049 additionalProperties: false
0050
0051 examples:
0052 - |
0053 topckgen: syscon@10000000 {
0054 compatible = "mediatek,mt8186-topckgen", "syscon";
0055 reg = <0x10000000 0x1000>;
0056 #clock-cells = <1>;
0057 };
