arm/mediatek/mediatek%2Cmt8186-clock.yaml

0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: MediaTek Functional Clock Controller for MT8186
0008
0009 maintainers:
0010   - Chun-Jie Chen <chun-jie.chen@mediatek.com>
0011
0012 description: |
0013   The clock architecture in MediaTek like below
0014   PLLs -->
0015           dividers -->
0016                       muxes
0017                            -->
0018                               clock gate
0019
0020   The devices provide clock gate control in different IP blocks.
0021
0022 properties:
0023   compatible:
0024     items:
0025       - enum:
0026           - mediatek,mt8186-imp_iic_wrap
0027           - mediatek,mt8186-mfgsys
0028           - mediatek,mt8186-wpesys
0029           - mediatek,mt8186-imgsys1
0030           - mediatek,mt8186-imgsys2
0031           - mediatek,mt8186-vdecsys
0032           - mediatek,mt8186-vencsys
0033           - mediatek,mt8186-camsys
0034           - mediatek,mt8186-camsys_rawa
0035           - mediatek,mt8186-camsys_rawb
0036           - mediatek,mt8186-mdpsys
0037           - mediatek,mt8186-ipesys
0038   reg:
0039     maxItems: 1
0040
0041   '#clock-cells':
0042     const: 1
0043
0044 required:
0045   - compatible
0046   - reg
0047
0048 additionalProperties: false
0049
0050 examples:
0051   - |
0052     imp_iic_wrap: clock-controller@11017000 {
0053         compatible = "mediatek,mt8186-imp_iic_wrap";
0054         reg = <0x11017000 0x1000>;
0055         #clock-cells = <1>;
0056     };