0001 Mediatek IPU controller
0002 ============================
0003
0004 The Mediatek ipu controller provides various clocks to the system.
0005
0006 Required Properties:
0007
0008 - compatible: Should be one of:
0009 - "mediatek,mt8183-ipu_conn", "syscon"
0010 - "mediatek,mt8183-ipu_adl", "syscon"
0011 - "mediatek,mt8183-ipu_core0", "syscon"
0012 - "mediatek,mt8183-ipu_core1", "syscon"
0013 - #clock-cells: Must be 1
0014
0015 The ipu controller uses the common clk binding from
0016 Documentation/devicetree/bindings/clock/clock-bindings.txt
0017 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
0018
0019 Example:
0020
0021 ipu_conn: syscon@19000000 {
0022 compatible = "mediatek,mt8183-ipu_conn", "syscon";
0023 reg = <0 0x19000000 0 0x1000>;
0024 #clock-cells = <1>;
0025 };
0026
0027 ipu_adl: syscon@19010000 {
0028 compatible = "mediatek,mt8183-ipu_adl", "syscon";
0029 reg = <0 0x19010000 0 0x1000>;
0030 #clock-cells = <1>;
0031 };
0032
0033 ipu_core0: syscon@19180000 {
0034 compatible = "mediatek,mt8183-ipu_core0", "syscon";
0035 reg = <0 0x19180000 0 0x1000>;
0036 #clock-cells = <1>;
0037 };
0038
0039 ipu_core1: syscon@19280000 {
0040 compatible = "mediatek,mt8183-ipu_core1", "syscon";
0041 reg = <0 0x19280000 0 0x1000>;
0042 #clock-cells = <1>;
0043 };
