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0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006 
0007 title: MediaTek Infrastructure System Configuration Controller
0008 
0009 maintainers:
0010   - Matthias Brugger <matthias.bgg@gmail.com>
0011 
0012 description:
0013   The Mediatek infracfg controller provides various clocks and reset outputs
0014   to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
0015   and reset values in <dt-bindings/reset/mt*-reset.h> and
0016   <dt-bindings/reset/mt*-resets.h>.
0017 
0018 properties:
0019   compatible:
0020     oneOf:
0021       - items:
0022           - enum:
0023               - mediatek,mt2701-infracfg
0024               - mediatek,mt2712-infracfg
0025               - mediatek,mt6765-infracfg
0026               - mediatek,mt6779-infracfg_ao
0027               - mediatek,mt6797-infracfg
0028               - mediatek,mt7622-infracfg
0029               - mediatek,mt7629-infracfg
0030               - mediatek,mt7986-infracfg
0031               - mediatek,mt8135-infracfg
0032               - mediatek,mt8167-infracfg
0033               - mediatek,mt8173-infracfg
0034               - mediatek,mt8183-infracfg
0035               - mediatek,mt8516-infracfg
0036           - const: syscon
0037       - items:
0038           - const: mediatek,mt7623-infracfg
0039           - const: mediatek,mt2701-infracfg
0040           - const: syscon
0041 
0042   reg:
0043     maxItems: 1
0044 
0045   '#clock-cells':
0046     const: 1
0047 
0048   '#reset-cells':
0049     const: 1
0050 
0051 required:
0052   - compatible
0053   - reg
0054   - '#clock-cells'
0055 
0056 if:
0057   properties:
0058     compatible:
0059       contains:
0060         enum:
0061           - mediatek,mt2701-infracfg
0062           - mediatek,mt2712-infracfg
0063           - mediatek,mt7622-infracfg
0064           - mediatek,mt7986-infracfg
0065           - mediatek,mt8135-infracfg
0066           - mediatek,mt8173-infracfg
0067           - mediatek,mt8183-infracfg
0068 then:
0069   required:
0070     - '#reset-cells'
0071 
0072 additionalProperties: false
0073 
0074 examples:
0075   - |
0076     infracfg: clock-controller@10001000 {
0077         compatible = "mediatek,mt8173-infracfg", "syscon";
0078         reg = <0x10001000 0x1000>;
0079         #clock-cells = <1>;
0080         #reset-cells = <1>;
0081     };