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OSCL-LXR

 
 

    


0001 Mediatek ethsys controller
0002 ============================
0003 
0004 The Mediatek ethsys controller provides various clocks to the system.
0005 
0006 Required Properties:
0007 
0008 - compatible: Should be:
0009         - "mediatek,mt2701-ethsys", "syscon"
0010         - "mediatek,mt7622-ethsys", "syscon"
0011         - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
0012         - "mediatek,mt7629-ethsys", "syscon"
0013         - "mediatek,mt7986-ethsys", "syscon"
0014 - #clock-cells: Must be 1
0015 - #reset-cells: Must be 1
0016 
0017 The ethsys controller uses the common clk binding from
0018 Documentation/devicetree/bindings/clock/clock-bindings.txt
0019 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
0020 
0021 Example:
0022 
0023 ethsys: clock-controller@1b000000 {
0024         compatible = "mediatek,mt2701-ethsys", "syscon";
0025         reg = <0 0x1b000000 0 0x1000>;
0026         #clock-cells = <1>;
0027         #reset-cells = <1>;
0028 };