0001 Marvell Armada CP110 System Controller
0002 ======================================
0003
0004 The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
0005 SoCs. It contains system controllers, which provide several registers
0006 giving access to numerous features: clocks, pin-muxing and many other
0007 SoC configuration items. This DT binding allows to describe these
0008 system controllers.
0009
0010 For the top level node:
0011 - compatible: must be: "syscon", "simple-mfd";
0012 - reg: register area of the CP110 system controller
0013
0014 SYSTEM CONTROLLER 0
0015 ===================
0016
0017 Clocks:
0018 -------
0019
0020 The Device Tree node representing this System Controller 0 provides a
0021 number of clocks:
0022
0023 - a set of core clocks
0024 - a set of gatable clocks
0025
0026 Those clocks can be referenced by other Device Tree nodes using two
0027 cells:
0028 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
0029 gatable clocks.
0030 - The second cell identifies the particular core clock or gatable
0031 clocks.
0032
0033 The following clocks are available:
0034 - Core clocks
0035 - 0 0 APLL
0036 - 0 1 PPv2 core
0037 - 0 2 EIP
0038 - 0 3 Core
0039 - 0 4 NAND core
0040 - 0 5 SDIO core
0041 - Gatable clocks
0042 - 1 0 Audio
0043 - 1 1 Comm Unit
0044 - 1 2 NAND
0045 - 1 3 PPv2
0046 - 1 4 SDIO
0047 - 1 5 MG Domain
0048 - 1 6 MG Core
0049 - 1 7 XOR1
0050 - 1 8 XOR0
0051 - 1 9 GOP DP
0052 - 1 11 PCIe x1 0
0053 - 1 12 PCIe x1 1
0054 - 1 13 PCIe x4
0055 - 1 14 PCIe / XOR
0056 - 1 15 SATA
0057 - 1 16 SATA USB
0058 - 1 17 Main
0059 - 1 18 SD/MMC/GOP
0060 - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
0061 - 1 22 USB3H0
0062 - 1 23 USB3H1
0063 - 1 24 USB3 Device
0064 - 1 25 EIP150
0065 - 1 26 EIP197
0066
0067 Required properties:
0068
0069 - compatible: must be:
0070 "marvell,cp110-clock"
0071 - #clock-cells: must be set to 2
0072
0073 Pinctrl:
0074 --------
0075
0076 For common binding part and usage, refer to the file
0077 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
0078
0079 Required properties:
0080
0081 - compatible: "marvell,armada-7k-pinctrl", "marvell,armada-8k-cpm-pinctrl",
0082 "marvell,armada-8k-cps-pinctrl" or "marvell,cp115-standalone-pinctrl"
0083 depending on the specific variant of the SoC being used.
0084
0085 Available mpp pins/groups and functions:
0086 Note: brackets (x) are not part of the mpp name for marvell,function and given
0087 only for more detailed description in this document.
0088
0089 name pins functions
0090 ================================================================================
0091 mpp0 0 gpio, dev(ale1), au(i2smclk), ge0(rxd3), tdm(pclk), ptp(pulse), mss_i2c(sda), uart0(rxd), sata0(present_act), ge(mdio)
0092 mpp1 1 gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), sata1(present_act), ge(mdc)
0093 mpp2 2 gpio, dev(ad15), au(i2sextclk), ge0(rxd1), tdm(dtx), mss_uart(rxd), ptp(pclk_out), i2c1(sck), uart1(rxd), sata0(present_act), xg(mdc)
0094 mpp3 3 gpio, dev(ad14), au(i2slrclk), ge0(rxd0), tdm(fsync), mss_uart(txd), pcie(rstoutn), i2c1(sda), uart1(txd), sata1(present_act), xg(mdio)
0095 mpp4 4 gpio, dev(ad13), au(i2sbclk), ge0(rxctl), tdm(rstn), mss_uart(rxd), uart1(cts), pcie0(clkreq), uart3(rxd), ge(mdc)
0096 mpp5 5 gpio, dev(ad12), au(i2sdi), ge0(rxclk), tdm(intn), mss_uart(txd), uart1(rts), pcie1(clkreq), uart3(txd), ge(mdio)
0097 mpp6 6 gpio, dev(ad11), ge0(txd3), spi0(csn2), au(i2sextclk), sata1(present_act), pcie2(clkreq), uart0(rxd), ptp(pulse)
0098 mpp7 7 gpio, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), sata0(present_act), led(data), uart0(txd), ptp(clk)
0099 mpp8 8 gpio, dev(ad9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), led(stb), uart2(rxd), ptp(pclk_out), synce1(clk)
0100 mpp9 9 gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), pcie(rstoutn), synce2(clk)
0101 mpp10 10 gpio, dev(readyn), ge0(txctl), spi0(miso), spi1(miso), uart0(cts), sata1(present_act)
0102 mpp11 11 gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), uart0(rts), led(clk), uart2(txd), sata0(present_act)
0103 mpp12 12 gpio, dev(clk_out), nf(rbn1), spi1(csn1), ge0(rxclk)
0104 mpp13 13 gpio, dev(burstn), nf(rbn0), spi1(miso), ge0(rxctl), mss_spi(miso)
0105 mpp14 14 gpio, dev(bootcsn), dev(csn0), spi1(csn0), spi0(csn3), au(i2sextclk), spi0(miso), sata0(present_act), mss_spi(csn)
0106 mpp15 15 gpio, dev(ad7), spi1(mosi), spi0(mosi), mss_spi(mosi), ptp(pulse_cp2cp)
0107 mpp16 16 gpio, dev(ad6), spi1(clk), mss_spi(clk)
0108 mpp17 17 gpio, dev(ad5), ge0(txd3)
0109 mpp18 18 gpio, dev(ad4), ge0(txd2), ptp(clk_cp2cp)
0110 mpp19 19 gpio, dev(ad3), ge0(txd1), wakeup(out_cp2cp)
0111 mpp20 20 gpio, dev(ad2), ge0(txd0)
0112 mpp21 21 gpio, dev(ad1), ge0(txctl), sei(in_cp2cp)
0113 mpp22 22 gpio, dev(ad0), ge0(txclkout), wakeup(in_cp2cp)
0114 mpp23 23 gpio, dev(a1), au(i2smclk), link(rd_in_cp2cp)
0115 mpp24 24 gpio, dev(a0), au(i2slrclk)
0116 mpp25 25 gpio, dev(oen), au(i2sdo_spdifo)
0117 mpp26 26 gpio, dev(wen0), au(i2sbclk)
0118 mpp27 27 gpio, dev(csn0), spi1(miso), mss_gpio4, ge0(rxd3), spi0(csn4), ge(mdio), sata0(present_act), uart0(rts), rei(in_cp2cp)
0119 mpp28 28 gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), ge(mdc), sata1(present_act), uart0(cts), led(data)
0120 mpp29 29 gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), pcie1(clkreq), ptp(clk), mss_i2c(sda), sata0(present_act), uart0(rxd), led(stb)
0121 mpp30 30 gpio, dev(csn3), spi1(clk), mss_gpio7, ge0(rxd0), spi0(csn7), pcie0(clkreq), ptp(pclk_out), mss_i2c(sck), sata1(present_act), uart0(txd), led(clk)
0122 mpp31 31 gpio, dev(a2), mss_gpio4, pcie(rstoutn), ge(mdc)
0123 mpp32 32 gpio, mii(col), mii(txerr), mss_spi(miso), tdm(drx), au(i2sextclk), au(i2sdi), ge(mdio), sdio(v18_en), pcie1(clkreq), mss_gpio0
0124 mpp33 33 gpio, mii(txclk), sdio(pwr10), mss_spi(csn), tdm(fsync), au(i2smclk), sdio(bus_pwr), xg(mdio), pcie2(clkreq), mss_gpio1
0125 mpp34 34 gpio, mii(rxerr), sdio(pwr11), mss_spi(mosi), tdm(dtx), au(i2slrclk), sdio(wr_protect), ge(mdc), pcie0(clkreq), mss_gpio2
0126 mpp35 35 gpio, sata1(present_act), i2c1(sda), mss_spi(clk), tdm(pclk), au(i2sdo_spdifo), sdio(card_detect), xg(mdio), ge(mdio), pcie(rstoutn), mss_gpio3
0127 mpp36 36 gpio, synce2(clk), i2c1(sck), ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(mdc), ge(mdc), pcie2(clkreq), mss_gpio5
0128 mpp37 37 gpio, uart2(rxd), i2c0(sck), ptp(pclk_out), tdm(intn), mss_i2c(sck), sata1(present_act), ge(mdc), xg(mdc), pcie1(clkreq), mss_gpio6, link(rd_out_cp2cp)
0129 mpp38 38 gpio, uart2(txd), i2c0(sda), ptp(pulse), tdm(rstn), mss_i2c(sda), sata0(present_act), ge(mdio), xg(mdio), au(i2sextclk), mss_gpio7, ptp(pulse_cp2cp)
0130 mpp39 39 gpio, sdio(wr_protect), au(i2sbclk), ptp(clk), spi0(csn1), sata1(present_act), mss_gpio0
0131 mpp40 40 gpio, sdio(pwr11), synce1(clk), mss_i2c(sda), au(i2sdo_spdifo), ptp(pclk_out), spi0(clk), uart1(txd), ge(mdio), sata0(present_act), mss_gpio1
0132 mpp41 41 gpio, sdio(pwr10), sdio(bus_pwr), mss_i2c(sck), au(i2slrclk), ptp(pulse), spi0(mosi), uart1(rxd), ge(mdc), sata1(present_act), mss_gpio2, rei(out_cp2cp)
0133 mpp42 42 gpio, sdio(v18_en), sdio(wr_protect), synce2(clk), au(i2smclk), mss_uart(txd), spi0(miso), uart1(cts), xg(mdc), sata0(present_act), mss_gpio4
0134 mpp43 43 gpio, sdio(card_detect), synce1(clk), au(i2sextclk), mss_uart(rxd), spi0(csn0), uart1(rts), xg(mdio), sata1(present_act), mss_gpio5, wakeup(out_cp2cp)
0135 mpp44 44 gpio, ge1(txd2), uart0(rts), ptp(clk_cp2cp)
0136 mpp45 45 gpio, ge1(txd3), uart0(txd), pcie(rstoutn)
0137 mpp46 46 gpio, ge1(txd1), uart1(rts)
0138 mpp47 47 gpio, ge1(txd0), spi1(clk), uart1(txd), ge(mdc)
0139 mpp48 48 gpio, ge1(txctl_txen), spi1(mosi), xg(mdc), wakeup(in_cp2cp)
0140 mpp49 49 gpio, ge1(txclkout), mii(crs), spi1(miso), uart1(rxd), ge(mdio), pcie0(clkreq), sdio(v18_en), sei(out_cp2cp)
0141 mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg(mdio), sdio(pwr11)
0142 mpp51 51 gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10)
0143 mpp52 52 gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq)
0144 mpp53 53 gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led)
0145 mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio_wp(wr_protect)
0146 mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio_cd(card_detect)
0147 mpp56 56 gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk)
0148 mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd)
0149 mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0)
0150 mpp59 59 gpio, mss_gpio7, synce2(clk), tdm(fsync), au(i2slrclk), spi0(csn0), uart0(cts), led(stb), uart1(txd), sdio(d1)
0151 mpp60 60 gpio, mss_gpio6, ptp(pulse), tdm(dtx), au(i2smclk), spi0(csn1), uart0(rts), led(data), uart1(rxd), sdio(d2)
0152 mpp61 61 gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), spi0(csn2), uart0(txd), uart2(txd), sata1(present_act), ge(mdio), sdio(d3)
0153 mpp62 62 gpio, mss_gpio4, synce1(clk), ptp(pclk_out), sata1(present_act), spi0(csn3), uart0(rxd), uart2(rxd), sata0(present_act), ge(mdc)
0154
0155 GPIO:
0156 -----
0157
0158 For common binding part and usage, refer to
0159 Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.
0160
0161 Required properties:
0162
0163 - compatible: "marvell,armada-8k-gpio"
0164
0165 - offset: offset address inside the syscon block
0166
0167 Example:
0168
0169 CP110_LABEL(syscon0): system-controller@440000 {
0170 compatible = "syscon", "simple-mfd";
0171 reg = <0x440000 0x1000>;
0172
0173 CP110_LABEL(clk): clock {
0174 compatible = "marvell,cp110-clock";
0175 #clock-cells = <2>;
0176 };
0177
0178 CP110_LABEL(pinctrl): pinctrl {
0179 compatible = "marvell,armada-8k-cpm-pinctrl";
0180 };
0181
0182 CP110_LABEL(gpio1): gpio@100 {
0183 compatible = "marvell,armada-8k-gpio";
0184 offset = <0x100>;
0185 ngpios = <32>;
0186 gpio-controller;
0187 #gpio-cells = <2>;
0188 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
0189 };
0190
0191 };
0192
0193 SYSTEM CONTROLLER 1
0194 ===================
0195
0196 Thermal:
0197 --------
0198
0199 The thermal IP can probe the temperature all around the processor. It
0200 may feature several channels, each of them wired to one sensor.
0201
0202 It is possible to setup an overheat interrupt by giving at least one
0203 critical point to any subnode of the thermal-zone node.
0204
0205 For common binding part and usage, refer to
0206 Documentation/devicetree/bindings/thermal/thermal*.yaml
0207
0208 Required properties:
0209 - compatible: must be one of:
0210 * marvell,armada-cp110-thermal
0211 - reg: register range associated with the thermal functions.
0212
0213 Optional properties:
0214 - interrupts-extended: overheat interrupt handle. Should point to
0215 a line of the ICU-SEI irqchip (116 is what is usually used by the
0216 firmware). The ICU-SEI will redirect towards interrupt line #37 of the
0217 AP SEI which is shared across all CPs.
0218 See interrupt-controller/interrupts.txt
0219 - #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
0220 to this IP and represents the channel ID. There is one sensor per
0221 channel. O refers to the thermal IP internal channel.
0222
0223 Example:
0224 CP110_LABEL(syscon1): system-controller@6f8000 {
0225 compatible = "syscon", "simple-mfd";
0226 reg = <0x6f8000 0x1000>;
0227
0228 CP110_LABEL(thermal): thermal-sensor@70 {
0229 compatible = "marvell,armada-cp110-thermal";
0230 reg = <0x70 0x10>;
0231 interrupts-extended = <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
0232 #thermal-sensor-cells = <1>;
0233 };
0234 };
