0001 Marvell Armada AP80x System Controller
0002 ======================================
0003
0004 The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
0005 7K/8K/931x SoCs. It contains system controllers, which provide several
0006 registers giving access to numerous features: clocks, pin-muxing and
0007 many other SoC configuration items. This DT binding allows to describe
0008 these system controllers.
0009
0010 For the top level node:
0011 - compatible: must be: "syscon", "simple-mfd";
0012 - reg: register area of the AP80x system controller
0013
0014 SYSTEM CONTROLLER 0
0015 ===================
0016
0017 Clocks:
0018 -------
0019
0020
0021 The Device Tree node representing the AP806/AP807 system controller
0022 provides a number of clocks:
0023
0024 - 0: reference clock of CPU cluster 0
0025 - 1: reference clock of CPU cluster 1
0026 - 2: fixed PLL at 1200 Mhz
0027 - 3: MSS clock, derived from the fixed PLL
0028
0029 Required properties:
0030
0031 - compatible: must be one of:
0032 * "marvell,ap806-clock"
0033 * "marvell,ap807-clock"
0034 - #clock-cells: must be set to 1
0035
0036 Pinctrl:
0037 --------
0038
0039 For common binding part and usage, refer to
0040 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
0041
0042 Required properties:
0043 - compatible must be "marvell,ap806-pinctrl",
0044
0045 Available mpp pins/groups and functions:
0046 Note: brackets (x) are not part of the mpp name for marvell,function and given
0047 only for more detailed description in this document.
0048
0049 name pins functions
0050 ================================================================================
0051 mpp0 0 gpio, sdio(clk), spi0(clk)
0052 mpp1 1 gpio, sdio(cmd), spi0(miso)
0053 mpp2 2 gpio, sdio(d0), spi0(mosi)
0054 mpp3 3 gpio, sdio(d1), spi0(cs0n)
0055 mpp4 4 gpio, sdio(d2), i2c0(sda)
0056 mpp5 5 gpio, sdio(d3), i2c0(sdk)
0057 mpp6 6 gpio, sdio(ds)
0058 mpp7 7 gpio, sdio(d4), uart1(rxd)
0059 mpp8 8 gpio, sdio(d5), uart1(txd)
0060 mpp9 9 gpio, sdio(d6), spi0(cs1n)
0061 mpp10 10 gpio, sdio(d7)
0062 mpp11 11 gpio, uart0(txd)
0063 mpp12 12 gpio, sdio(pw_off), sdio(hw_rst)
0064 mpp13 13 gpio
0065 mpp14 14 gpio
0066 mpp15 15 gpio
0067 mpp16 16 gpio
0068 mpp17 17 gpio
0069 mpp18 18 gpio
0070 mpp19 19 gpio, uart0(rxd), sdio(pw_off)
0071
0072 GPIO:
0073 -----
0074 For common binding part and usage, refer to
0075 Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.
0076
0077 Required properties:
0078
0079 - compatible: "marvell,armada-8k-gpio"
0080
0081 - offset: offset address inside the syscon block
0082
0083 Optional properties:
0084
0085 - marvell,pwm-offset: offset address of PWM duration control registers inside
0086 the syscon block
0087
0088 Example:
0089 ap_syscon: system-controller@6f4000 {
0090 compatible = "syscon", "simple-mfd";
0091 reg = <0x6f4000 0x1000>;
0092
0093 ap_clk: clock {
0094 compatible = "marvell,ap806-clock";
0095 #clock-cells = <1>;
0096 };
0097
0098 ap_pinctrl: pinctrl {
0099 compatible = "marvell,ap806-pinctrl";
0100 };
0101
0102 ap_gpio: gpio {
0103 compatible = "marvell,armada-8k-gpio";
0104 offset = <0x1040>;
0105 ngpios = <19>;
0106 gpio-controller;
0107 #gpio-cells = <2>;
0108 gpio-ranges = <&ap_pinctrl 0 0 19>;
0109 marvell,pwm-offset = <0x10c0>;
0110 #pwm-cells = <2>;
0111 clocks = <&ap_clk 3>;
0112 };
0113 };
0114
0115 SYSTEM CONTROLLER 1
0116 ===================
0117
0118 Thermal:
0119 --------
0120
0121 For common binding part and usage, refer to
0122 Documentation/devicetree/bindings/thermal/thermal*.yaml
0123
0124 The thermal IP can probe the temperature all around the processor. It
0125 may feature several channels, each of them wired to one sensor.
0126
0127 It is possible to setup an overheat interrupt by giving at least one
0128 critical point to any subnode of the thermal-zone node.
0129
0130 Required properties:
0131 - compatible: must be one of:
0132 * marvell,armada-ap806-thermal
0133 - reg: register range associated with the thermal functions.
0134
0135 Optional properties:
0136 - interrupts: overheat interrupt handle. Should point to line 18 of the
0137 SEI irqchip. See interrupt-controller/interrupts.txt
0138 - #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
0139 to this IP and represents the channel ID. There is one sensor per
0140 channel. O refers to the thermal IP internal channel, while positive
0141 IDs refer to each CPU.
0142
0143 Example:
0144 ap_syscon1: system-controller@6f8000 {
0145 compatible = "syscon", "simple-mfd";
0146 reg = <0x6f8000 0x1000>;
0147
0148 ap_thermal: thermal-sensor@80 {
0149 compatible = "marvell,armada-ap806-thermal";
0150 reg = <0x80 0x10>;
0151 interrupt-parent = <&sei>;
0152 interrupts = <18>;
0153 #thermal-sensor-cells = <1>;
0154 };
0155 };
0156
0157 Cluster clocks:
0158 ---------------
0159
0160 Device Tree Clock bindings for cluster clock of Marvell
0161 AP806/AP807. Each cluster contain up to 2 CPUs running at the same
0162 frequency.
0163
0164 Required properties:
0165 - compatible: must be one of:
0166 * "marvell,ap806-cpu-clock"
0167 * "marvell,ap807-cpu-clock"
0168 - #clock-cells : should be set to 1.
0169
0170 - clocks : shall be the input parent clock(s) phandle for the clock
0171 (one per cluster)
0172
0173 - reg: register range associated with the cluster clocks
0174
0175 ap_syscon1: system-controller@6f8000 {
0176 compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
0177 reg = <0x6f8000 0x1000>;
0178
0179 cpu_clk: clock-cpu@278 {
0180 compatible = "marvell,ap806-cpu-clock";
0181 clocks = <&ap_clk 0>, <&ap_clk 1>;
0182 #clock-cells = <1>;
0183 reg = <0x278 0xa30>;
0184 };
0185 };
