0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM L2 Cache Controller
0008
0009 maintainers:
0010 - Rob Herring <robh@kernel.org>
0011
0012 description: |+
0013 ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
0014 PL220/PL310 and variants) based level 2 cache controller. All these various
0015 implementations of the L2 cache controller have compatible programming
0016 models (Note 1). Some of the properties that are just prefixed "cache-*" are
0017 taken from section 3.7.3 of the Devicetree Specification which can be found
0018 at:
0019 https://www.devicetree.org/specifications/
0020
0021 Note 1: The description in this document doesn't apply to integrated L2
0022 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
0023 integrated L2 controllers are assumed to be all preconfigured by
0024 early secure boot code. Thus no need to deal with their configuration
0025 in the kernel at all.
0026
0027 allOf:
0028 - $ref: /schemas/cache-controller.yaml#
0029
0030 properties:
0031 compatible:
0032 oneOf:
0033 - enum:
0034 - arm,pl310-cache
0035 - arm,l220-cache
0036 - arm,l210-cache
0037 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
0038 - bcm,bcm11351-a2-pl310-cache
0039 # For Broadcom bcm11351 chipset where an
0040 # offset needs to be added to the address before passing down to the L2
0041 # cache controller
0042 - brcm,bcm11351-a2-pl310-cache
0043 # Marvell Controller designed to be
0044 # compatible with the ARM one, with system cache mode (meaning
0045 # maintenance operations on L1 are broadcasted to the L2 and L2
0046 # performs the same operation).
0047 - marvell,aurora-system-cache
0048 # Marvell Controller designed to be
0049 # compatible with the ARM one with outer cache mode.
0050 - marvell,aurora-outer-cache
0051 - items:
0052 # Marvell Tauros3 cache controller, compatible
0053 # with arm,pl310-cache controller.
0054 - const: marvell,tauros3-cache
0055 - const: arm,pl310-cache
0056
0057 cache-level:
0058 const: 2
0059
0060 cache-unified: true
0061 cache-size: true
0062 cache-sets: true
0063 cache-block-size: true
0064 cache-line-size: true
0065
0066 reg:
0067 maxItems: 1
0068
0069 arm,data-latency:
0070 description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
0071 read, write and setup latencies. Minimum valid values are 1. Controllers
0072 without setup latency control should use a value of 0.
0073 $ref: /schemas/types.yaml#/definitions/uint32-array
0074 minItems: 2
0075 maxItems: 3
0076 items:
0077 minimum: 0
0078 maximum: 8
0079
0080 arm,tag-latency:
0081 description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
0082 read, write and setup latencies. Controllers without setup latency control
0083 should use 0. Controllers without separate read and write Tag RAM latency
0084 values should only use the first cell.
0085 $ref: /schemas/types.yaml#/definitions/uint32-array
0086 minItems: 1
0087 maxItems: 3
0088 items:
0089 minimum: 0
0090 maximum: 8
0091
0092 arm,dirty-latency:
0093 description: Cycles of latency for Dirty RAMs. This is a single cell.
0094 $ref: /schemas/types.yaml#/definitions/uint32
0095 minimum: 1
0096 maximum: 8
0097
0098 arm,filter-ranges:
0099 description: <start length> Starting address and length of window to
0100 filter. Addresses in the filter window are directed to the M1 port. Other
0101 addresses will go to the M0 port.
0102 $ref: /schemas/types.yaml#/definitions/uint32-array
0103 items:
0104 minItems: 2
0105 maxItems: 2
0106
0107 arm,io-coherent:
0108 description: indicates that the system is operating in an hardware
0109 I/O coherent mode. Valid only when the arm,pl310-cache compatible
0110 string is used.
0111 type: boolean
0112
0113 interrupts:
0114 # Either a single combined interrupt or up to 9 individual interrupts
0115 minItems: 1
0116 maxItems: 9
0117
0118 cache-id-part:
0119 description: cache id part number to be used if it is not present
0120 on hardware
0121 $ref: /schemas/types.yaml#/definitions/uint32
0122
0123 wt-override:
0124 description: If present then L2 is forced to Write through mode
0125 type: boolean
0126
0127 arm,double-linefill:
0128 description: Override double linefill enable setting. Enable if
0129 non-zero, disable if zero.
0130 $ref: /schemas/types.yaml#/definitions/uint32
0131 enum: [0, 1]
0132
0133 arm,double-linefill-incr:
0134 description: Override double linefill on INCR read. Enable
0135 if non-zero, disable if zero.
0136 $ref: /schemas/types.yaml#/definitions/uint32
0137 enum: [0, 1]
0138
0139 arm,double-linefill-wrap:
0140 description: Override double linefill on WRAP read. Enable
0141 if non-zero, disable if zero.
0142 $ref: /schemas/types.yaml#/definitions/uint32
0143 enum: [0, 1]
0144
0145 arm,prefetch-drop:
0146 description: Override prefetch drop enable setting. Enable if non-zero,
0147 disable if zero.
0148 $ref: /schemas/types.yaml#/definitions/uint32
0149 enum: [0, 1]
0150
0151 arm,prefetch-offset:
0152 description: Override prefetch offset value.
0153 $ref: /schemas/types.yaml#/definitions/uint32
0154 enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]
0155
0156 arm,shared-override:
0157 description: The default behavior of the L220 or PL310 cache
0158 controllers with respect to the shareable attribute is to transform "normal
0159 memory non-cacheable transactions" into "cacheable no allocate" (for reads)
0160 or "write through no write allocate" (for writes).
0161 On systems where this may cause DMA buffer corruption, this property must
0162 be specified to indicate that such transforms are precluded.
0163 type: boolean
0164
0165 arm,parity-enable:
0166 description: enable parity checking on the L2 cache (L220 or PL310).
0167 type: boolean
0168
0169 arm,parity-disable:
0170 description: disable parity checking on the L2 cache (L220 or PL310).
0171 type: boolean
0172
0173 marvell,ecc-enable:
0174 description: enable ECC protection on the L2 cache
0175 type: boolean
0176
0177 arm,outer-sync-disable:
0178 description: disable the outer sync operation on the L2 cache.
0179 Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
0180 will randomly hang unless outer sync operations are disabled.
0181 type: boolean
0182
0183 prefetch-data:
0184 description: |
0185 Data prefetch. Value: <0> (forcibly disable), <1>
0186 (forcibly enable), property absent (retain settings set by firmware)
0187 $ref: /schemas/types.yaml#/definitions/uint32
0188 enum: [0, 1]
0189
0190 prefetch-instr:
0191 description: |
0192 Instruction prefetch. Value: <0> (forcibly disable),
0193 <1> (forcibly enable), property absent (retain settings set by
0194 firmware)
0195 $ref: /schemas/types.yaml#/definitions/uint32
0196 enum: [0, 1]
0197
0198 arm,dynamic-clock-gating:
0199 description: |
0200 L2 dynamic clock gating. Value: <0> (forcibly
0201 disable), <1> (forcibly enable), property absent (OS specific behavior,
0202 preferably retain firmware settings)
0203 $ref: /schemas/types.yaml#/definitions/uint32
0204 enum: [0, 1]
0205
0206 arm,standby-mode:
0207 description: L2 standby mode enable. Value <0> (forcibly disable),
0208 <1> (forcibly enable), property absent (OS specific behavior,
0209 preferably retain firmware settings)
0210 $ref: /schemas/types.yaml#/definitions/uint32
0211 enum: [0, 1]
0212
0213 arm,early-bresp-disable:
0214 description: Disable the CA9 optimization Early BRESP (PL310)
0215 type: boolean
0216
0217 arm,full-line-zero-disable:
0218 description: Disable the CA9 optimization Full line of zero
0219 write (PL310)
0220 type: boolean
0221
0222 required:
0223 - compatible
0224 - cache-unified
0225 - reg
0226
0227 additionalProperties: false
0228
0229 examples:
0230 - |
0231 cache-controller@fff12000 {
0232 compatible = "arm,pl310-cache";
0233 reg = <0xfff12000 0x1000>;
0234 arm,data-latency = <1 1 1>;
0235 arm,tag-latency = <2 2 2>;
0236 arm,filter-ranges = <0x80000000 0x8000000>;
0237 cache-unified;
0238 cache-level = <2>;
0239 interrupts = <45>;
0240 };
0241
0242 ...
