0001 Freescale Vybrid Miscellaneous System Control - Interrupt Router
0002
0003 The MSCM IP contains multiple sub modules, this binding describes the second
0004 block of registers which control the interrupt router. The interrupt router
0005 allows to configure the recipient of each peripheral interrupt. Furthermore
0006 it controls the directed processor interrupts. The module is available in all
0007 Vybrid SoC's but is only really useful in dual core configurations (VF6xx
0008 which comes with a Cortex-A5/Cortex-M4 combination).
0009
0010 Required properties:
0011 - compatible: "fsl,vf610-mscm-ir"
0012 - reg: the register range of the MSCM Interrupt Router
0013 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
0014 to get the current CPU ID
0015 - interrupt-controller: Identifies the node as an interrupt controller
0016 - #interrupt-cells: Two cells, interrupt number and cells.
0017 The hardware interrupt number according to interrupt
0018 assignment of the interrupt router is required.
0019 Flags get passed only when using GIC as parent. Flags
0020 encoding as documented by the GIC bindings.
0021
0022 Example:
0023 mscm_ir: interrupt-controller@40001800 {
0024 compatible = "fsl,vf610-mscm-ir";
0025 reg = <0x40001800 0x400>;
0026 fsl,cpucfg = <&mscm_cpucfg>;
0027 interrupt-controller;
0028 #interrupt-cells = <2>;
0029 interrupt-parent = <&intc>;
0030 }
