0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/cpus.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM CPUs bindings
0008
0009 maintainers:
0010 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
0011
0012 description: |+
0013 The device tree allows to describe the layout of CPUs in a system through
0014 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
0015 defining properties for every cpu.
0016
0017 Bindings for CPU nodes follow the Devicetree Specification, available from:
0018
0019 https://www.devicetree.org/specifications/
0020
0021 with updates for 32-bit and 64-bit ARM systems provided in this document.
0022
0023 ================================
0024 Convention used in this document
0025 ================================
0026
0027 This document follows the conventions described in the Devicetree
0028 Specification, with the addition:
0029
0030 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
0031 the reg property contained in bits 7 down to 0
0032
0033 =====================================
0034 cpus and cpu node bindings definition
0035 =====================================
0036
0037 The ARM architecture, in accordance with the Devicetree Specification,
0038 requires the cpus and cpu nodes to be present and contain the properties
0039 described below.
0040
0041 properties:
0042 reg:
0043 maxItems: 1
0044 description: |
0045 Usage and definition depend on ARM architecture version and
0046 configuration:
0047
0048 On uniprocessor ARM architectures previous to v7
0049 this property is required and must be set to 0.
0050
0051 On ARM 11 MPcore based systems this property is
0052 required and matches the CPUID[11:0] register bits.
0053
0054 Bits [11:0] in the reg cell must be set to
0055 bits [11:0] in CPU ID register.
0056
0057 All other bits in the reg cell must be set to 0.
0058
0059 On 32-bit ARM v7 or later systems this property is
0060 required and matches the CPU MPIDR[23:0] register
0061 bits.
0062
0063 Bits [23:0] in the reg cell must be set to
0064 bits [23:0] in MPIDR.
0065
0066 All other bits in the reg cell must be set to 0.
0067
0068 On ARM v8 64-bit systems this property is required
0069 and matches the MPIDR_EL1 register affinity bits.
0070
0071 * If cpus node's #address-cells property is set to 2
0072
0073 The first reg cell bits [7:0] must be set to
0074 bits [39:32] of MPIDR_EL1.
0075
0076 The second reg cell bits [23:0] must be set to
0077 bits [23:0] of MPIDR_EL1.
0078
0079 * If cpus node's #address-cells property is set to 1
0080
0081 The reg cell bits [23:0] must be set to bits [23:0]
0082 of MPIDR_EL1.
0083
0084 All other bits in the reg cells must be set to 0.
0085
0086 compatible:
0087 enum:
0088 - apple,icestorm
0089 - apple,firestorm
0090 - arm,arm710t
0091 - arm,arm720t
0092 - arm,arm740t
0093 - arm,arm7ej-s
0094 - arm,arm7tdmi
0095 - arm,arm7tdmi-s
0096 - arm,arm9es
0097 - arm,arm9ej-s
0098 - arm,arm920t
0099 - arm,arm922t
0100 - arm,arm925
0101 - arm,arm926e-s
0102 - arm,arm926ej-s
0103 - arm,arm940t
0104 - arm,arm946e-s
0105 - arm,arm966e-s
0106 - arm,arm968e-s
0107 - arm,arm9tdmi
0108 - arm,arm1020e
0109 - arm,arm1020t
0110 - arm,arm1022e
0111 - arm,arm1026ej-s
0112 - arm,arm1136j-s
0113 - arm,arm1136jf-s
0114 - arm,arm1156t2-s
0115 - arm,arm1156t2f-s
0116 - arm,arm1176jzf
0117 - arm,arm1176jz-s
0118 - arm,arm1176jzf-s
0119 - arm,arm11mpcore
0120 - arm,armv8 # Only for s/w models
0121 - arm,cortex-a5
0122 - arm,cortex-a7
0123 - arm,cortex-a8
0124 - arm,cortex-a9
0125 - arm,cortex-a12
0126 - arm,cortex-a15
0127 - arm,cortex-a17
0128 - arm,cortex-a32
0129 - arm,cortex-a34
0130 - arm,cortex-a35
0131 - arm,cortex-a53
0132 - arm,cortex-a55
0133 - arm,cortex-a57
0134 - arm,cortex-a65
0135 - arm,cortex-a72
0136 - arm,cortex-a73
0137 - arm,cortex-a75
0138 - arm,cortex-a76
0139 - arm,cortex-a77
0140 - arm,cortex-a78
0141 - arm,cortex-a78ae
0142 - arm,cortex-a510
0143 - arm,cortex-a710
0144 - arm,cortex-m0
0145 - arm,cortex-m0+
0146 - arm,cortex-m1
0147 - arm,cortex-m3
0148 - arm,cortex-m4
0149 - arm,cortex-r4
0150 - arm,cortex-r5
0151 - arm,cortex-r7
0152 - arm,cortex-x1
0153 - arm,cortex-x2
0154 - arm,neoverse-e1
0155 - arm,neoverse-n1
0156 - arm,neoverse-n2
0157 - arm,neoverse-v1
0158 - brcm,brahma-b15
0159 - brcm,brahma-b53
0160 - brcm,vulcan
0161 - cavium,thunder
0162 - cavium,thunder2
0163 - faraday,fa526
0164 - intel,sa110
0165 - intel,sa1100
0166 - marvell,feroceon
0167 - marvell,mohawk
0168 - marvell,pj4a
0169 - marvell,pj4b
0170 - marvell,sheeva-v5
0171 - marvell,sheeva-v7
0172 - nvidia,tegra132-denver
0173 - nvidia,tegra186-denver
0174 - nvidia,tegra194-carmel
0175 - qcom,krait
0176 - qcom,kryo
0177 - qcom,kryo250
0178 - qcom,kryo260
0179 - qcom,kryo280
0180 - qcom,kryo385
0181 - qcom,kryo468
0182 - qcom,kryo485
0183 - qcom,kryo560
0184 - qcom,kryo570
0185 - qcom,kryo685
0186 - qcom,kryo780
0187 - qcom,scorpion
0188
0189 enable-method:
0190 $ref: '/schemas/types.yaml#/definitions/string'
0191 oneOf:
0192 # On ARM v8 64-bit this property is required
0193 - enum:
0194 - psci
0195 - spin-table
0196 # On ARM 32-bit systems this property is optional
0197 - enum:
0198 - actions,s500-smp
0199 - allwinner,sun6i-a31
0200 - allwinner,sun8i-a23
0201 - allwinner,sun9i-a80-smp
0202 - allwinner,sun8i-a83t-smp
0203 - amlogic,meson8-smp
0204 - amlogic,meson8b-smp
0205 - arm,realview-smp
0206 - aspeed,ast2600-smp
0207 - brcm,bcm11351-cpu-method
0208 - brcm,bcm23550
0209 - brcm,bcm2836-smp
0210 - brcm,bcm63138
0211 - brcm,bcm-nsp-smp
0212 - brcm,brahma-b15
0213 - marvell,armada-375-smp
0214 - marvell,armada-380-smp
0215 - marvell,armada-390-smp
0216 - marvell,armada-xp-smp
0217 - marvell,98dx3236-smp
0218 - marvell,mmp3-smp
0219 - mediatek,mt6589-smp
0220 - mediatek,mt81xx-tz-smp
0221 - qcom,gcc-msm8660
0222 - qcom,kpss-acc-v1
0223 - qcom,kpss-acc-v2
0224 - qcom,msm8226-smp
0225 - qcom,msm8909-smp
0226 # Only valid on ARM 32-bit, see above for ARM v8 64-bit
0227 - qcom,msm8916-smp
0228 - renesas,apmu
0229 - renesas,r9a06g032-smp
0230 - rockchip,rk3036-smp
0231 - rockchip,rk3066-smp
0232 - socionext,milbeaut-m10v-smp
0233 - ste,dbx500-smp
0234 - ti,am3352
0235 - ti,am4372
0236
0237 cpu-release-addr:
0238 oneOf:
0239 - $ref: '/schemas/types.yaml#/definitions/uint32'
0240 - $ref: '/schemas/types.yaml#/definitions/uint64'
0241 description:
0242 The DT specification defines this as 64-bit always, but some 32-bit Arm
0243 systems have used a 32-bit value which must be supported.
0244 Required for systems that have an "enable-method"
0245 property value of "spin-table".
0246
0247 cpu-idle-states:
0248 $ref: '/schemas/types.yaml#/definitions/phandle-array'
0249 items:
0250 maxItems: 1
0251 description: |
0252 List of phandles to idle state nodes supported
0253 by this cpu (see ./idle-states.yaml).
0254
0255 capacity-dmips-mhz:
0256 description:
0257 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
0258 DMIPS/MHz, relative to highest capacity-dmips-mhz
0259 in the system.
0260
0261 cci-control-port: true
0262
0263 dynamic-power-coefficient:
0264 $ref: '/schemas/types.yaml#/definitions/uint32'
0265 description:
0266 A u32 value that represents the running time dynamic
0267 power coefficient in units of uW/MHz/V^2. The
0268 coefficient can either be calculated from power
0269 measurements or derived by analysis.
0270
0271 The dynamic power consumption of the CPU is
0272 proportional to the square of the Voltage (V) and
0273 the clock frequency (f). The coefficient is used to
0274 calculate the dynamic power as below -
0275
0276 Pdyn = dynamic-power-coefficient * V^2 * f
0277
0278 where voltage is in V, frequency is in MHz.
0279
0280 performance-domains:
0281 maxItems: 1
0282 description:
0283 List of phandles and performance domain specifiers, as defined by
0284 bindings of the performance domain provider. See also
0285 dvfs/performance-domain.yaml.
0286
0287 power-domains:
0288 description:
0289 List of phandles and PM domain specifiers, as defined by bindings of the
0290 PM domain provider (see also ../power_domain.txt).
0291
0292 power-domain-names:
0293 description:
0294 A list of power domain name strings sorted in the same order as the
0295 power-domains property.
0296
0297 For PSCI based platforms, the name corresponding to the index of the PSCI
0298 PM domain provider, must be "psci".
0299
0300 qcom,saw:
0301 $ref: '/schemas/types.yaml#/definitions/phandle'
0302 description: |
0303 Specifies the SAW* node associated with this CPU.
0304
0305 Required for systems that have an "enable-method" property
0306 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
0307
0308 * arm/msm/qcom,saw2.txt
0309
0310 qcom,acc:
0311 $ref: '/schemas/types.yaml#/definitions/phandle'
0312 description: |
0313 Specifies the ACC* node associated with this CPU.
0314
0315 Required for systems that have an "enable-method" property
0316 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
0317 "qcom,msm8916-smp".
0318
0319 * arm/msm/qcom,kpss-acc.txt
0320
0321 rockchip,pmu:
0322 $ref: '/schemas/types.yaml#/definitions/phandle'
0323 description: |
0324 Specifies the syscon node controlling the cpu core power domains.
0325
0326 Optional for systems that have an "enable-method"
0327 property value of "rockchip,rk3066-smp"
0328 While optional, it is the preferred way to get access to
0329 the cpu-core power-domains.
0330
0331 secondary-boot-reg:
0332 $ref: '/schemas/types.yaml#/definitions/uint32'
0333 description: |
0334 Required for systems that have an "enable-method" property value of
0335 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
0336
0337 This includes the following SoCs: |
0338 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
0339 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
0340
0341 The secondary-boot-reg property is a u32 value that specifies the
0342 physical address of the register used to request the ROM holding pen
0343 code release a secondary CPU. The value written to the register is
0344 formed by encoding the target CPU id into the low bits of the
0345 physical start address it should jump to.
0346
0347 if:
0348 # If the enable-method property contains one of those values
0349 properties:
0350 enable-method:
0351 contains:
0352 enum:
0353 - brcm,bcm11351-cpu-method
0354 - brcm,bcm23550
0355 - brcm,bcm-nsp-smp
0356 # and if enable-method is present
0357 required:
0358 - enable-method
0359
0360 then:
0361 required:
0362 - secondary-boot-reg
0363
0364 required:
0365 - device_type
0366 - reg
0367 - compatible
0368
0369 dependencies:
0370 rockchip,pmu: [enable-method]
0371
0372 additionalProperties: true
0373
0374 examples:
0375 - |
0376 cpus {
0377 #size-cells = <0>;
0378 #address-cells = <1>;
0379
0380 cpu@0 {
0381 device_type = "cpu";
0382 compatible = "arm,cortex-a15";
0383 reg = <0x0>;
0384 };
0385
0386 cpu@1 {
0387 device_type = "cpu";
0388 compatible = "arm,cortex-a15";
0389 reg = <0x1>;
0390 };
0391
0392 cpu@100 {
0393 device_type = "cpu";
0394 compatible = "arm,cortex-a7";
0395 reg = <0x100>;
0396 };
0397
0398 cpu@101 {
0399 device_type = "cpu";
0400 compatible = "arm,cortex-a7";
0401 reg = <0x101>;
0402 };
0403 };
0404
0405 - |
0406 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
0407 cpus {
0408 #size-cells = <0>;
0409 #address-cells = <1>;
0410
0411 cpu@0 {
0412 device_type = "cpu";
0413 compatible = "arm,cortex-a8";
0414 reg = <0x0>;
0415 };
0416 };
0417
0418 - |
0419 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
0420 cpus {
0421 #size-cells = <0>;
0422 #address-cells = <1>;
0423
0424 cpu@0 {
0425 device_type = "cpu";
0426 compatible = "arm,arm926ej-s";
0427 reg = <0x0>;
0428 };
0429 };
0430
0431 - |
0432 // Example 4 (ARM Cortex-A57 64-bit system):
0433 cpus {
0434 #size-cells = <0>;
0435 #address-cells = <2>;
0436
0437 cpu@0 {
0438 device_type = "cpu";
0439 compatible = "arm,cortex-a57";
0440 reg = <0x0 0x0>;
0441 enable-method = "spin-table";
0442 cpu-release-addr = <0 0x20000000>;
0443 };
0444
0445 cpu@1 {
0446 device_type = "cpu";
0447 compatible = "arm,cortex-a57";
0448 reg = <0x0 0x1>;
0449 enable-method = "spin-table";
0450 cpu-release-addr = <0 0x20000000>;
0451 };
0452
0453 cpu@100 {
0454 device_type = "cpu";
0455 compatible = "arm,cortex-a57";
0456 reg = <0x0 0x100>;
0457 enable-method = "spin-table";
0458 cpu-release-addr = <0 0x20000000>;
0459 };
0460
0461 cpu@101 {
0462 device_type = "cpu";
0463 compatible = "arm,cortex-a57";
0464 reg = <0x0 0x101>;
0465 enable-method = "spin-table";
0466 cpu-release-addr = <0 0x20000000>;
0467 };
0468
0469 cpu@10000 {
0470 device_type = "cpu";
0471 compatible = "arm,cortex-a57";
0472 reg = <0x0 0x10000>;
0473 enable-method = "spin-table";
0474 cpu-release-addr = <0 0x20000000>;
0475 };
0476
0477 cpu@10001 {
0478 device_type = "cpu";
0479 compatible = "arm,cortex-a57";
0480 reg = <0x0 0x10001>;
0481 enable-method = "spin-table";
0482 cpu-release-addr = <0 0x20000000>;
0483 };
0484
0485 cpu@10100 {
0486 device_type = "cpu";
0487 compatible = "arm,cortex-a57";
0488 reg = <0x0 0x10100>;
0489 enable-method = "spin-table";
0490 cpu-release-addr = <0 0x20000000>;
0491 };
0492
0493 cpu@10101 {
0494 device_type = "cpu";
0495 compatible = "arm,cortex-a57";
0496 reg = <0x0 0x10101>;
0497 enable-method = "spin-table";
0498 cpu-release-addr = <0 0x20000000>;
0499 };
0500
0501 cpu@100000000 {
0502 device_type = "cpu";
0503 compatible = "arm,cortex-a57";
0504 reg = <0x1 0x0>;
0505 enable-method = "spin-table";
0506 cpu-release-addr = <0 0x20000000>;
0507 };
0508
0509 cpu@100000001 {
0510 device_type = "cpu";
0511 compatible = "arm,cortex-a57";
0512 reg = <0x1 0x1>;
0513 enable-method = "spin-table";
0514 cpu-release-addr = <0 0x20000000>;
0515 };
0516
0517 cpu@100000100 {
0518 device_type = "cpu";
0519 compatible = "arm,cortex-a57";
0520 reg = <0x1 0x100>;
0521 enable-method = "spin-table";
0522 cpu-release-addr = <0 0x20000000>;
0523 };
0524
0525 cpu@100000101 {
0526 device_type = "cpu";
0527 compatible = "arm,cortex-a57";
0528 reg = <0x1 0x101>;
0529 enable-method = "spin-table";
0530 cpu-release-addr = <0 0x20000000>;
0531 };
0532
0533 cpu@100010000 {
0534 device_type = "cpu";
0535 compatible = "arm,cortex-a57";
0536 reg = <0x1 0x10000>;
0537 enable-method = "spin-table";
0538 cpu-release-addr = <0 0x20000000>;
0539 };
0540
0541 cpu@100010001 {
0542 device_type = "cpu";
0543 compatible = "arm,cortex-a57";
0544 reg = <0x1 0x10001>;
0545 enable-method = "spin-table";
0546 cpu-release-addr = <0 0x20000000>;
0547 };
0548
0549 cpu@100010100 {
0550 device_type = "cpu";
0551 compatible = "arm,cortex-a57";
0552 reg = <0x1 0x10100>;
0553 enable-method = "spin-table";
0554 cpu-release-addr = <0 0x20000000>;
0555 };
0556
0557 cpu@100010101 {
0558 device_type = "cpu";
0559 compatible = "arm,cortex-a57";
0560 reg = <0x1 0x10101>;
0561 enable-method = "spin-table";
0562 cpu-release-addr = <0 0x20000000>;
0563 };
0564 };
0565 ...
