0001 ==========================================
0002 ARM CPUs capacity bindings
0003 ==========================================
0004
0005 ==========================================
0006 1 - Introduction
0007 ==========================================
0008
0009 ARM systems may be configured to have cpus with different power/performance
0010 characteristics within the same chip. In this case, additional information has
0011 to be made available to the kernel for it to be aware of such differences and
0012 take decisions accordingly.
0013
0014 ==========================================
0015 2 - CPU capacity definition
0016 ==========================================
0017
0018 CPU capacity is a number that provides the scheduler information about CPUs
0019 heterogeneity. Such heterogeneity can come from micro-architectural differences
0020 (e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run
0021 (e.g., SMP systems with multiple frequency domains). Heterogeneity in this
0022 context is about differing performance characteristics; this binding tries to
0023 capture a first-order approximation of the relative performance of CPUs.
0024
0025 CPU capacities are obtained by running a suitable benchmark. This binding makes
0026 no guarantees on the validity or suitability of any particular benchmark, the
0027 final capacity should, however, be:
0028
0029 * A "single-threaded" or CPU affine benchmark
0030 * Divided by the running frequency of the CPU executing the benchmark
0031 * Not subject to dynamic frequency scaling of the CPU
0032
0033 For the time being we however advise usage of the Dhrystone benchmark. What
0034 above thus becomes:
0035
0036 CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
0037 max frequency (with caches enabled). The obtained DMIPS score is then divided
0038 by the frequency (in MHz) at which the benchmark has been run, so that
0039 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
0040 score obtained in the system.
0041
0042 ==========================================
0043 3 - capacity-dmips-mhz
0044 ==========================================
0045
0046 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
0047 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
0048 maximum frequency available to the cpu is then used to calculate the capacity
0049 value internally used by the kernel.
0050
0051 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
0052 node, it has to be specified for every other cpu nodes, or the system will
0053 fall back to the default capacity value for every CPU. If cpufreq is not
0054 available, final capacities are calculated by directly using capacity-dmips-
0055 mhz values (normalized w.r.t. the highest value found while parsing the DT).
0056
0057 ===========================================
0058 4 - Examples
0059 ===========================================
0060
0061 Example 1 (ARM 64-bit, 6-cpu system, two clusters):
0062 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
0063 are 1024 and 578 for cluster0 and cluster1. Further normalization
0064 is done by the operating system based on cluster0@max-freq=1100 and
0065 cluster1@max-freq=850, final capacities are 1024 for cluster0 and
0066 446 for cluster1 (578*850/1100).
0067
0068 cpus {
0069 #address-cells = <2>;
0070 #size-cells = <0>;
0071
0072 cpu-map {
0073 cluster0 {
0074 core0 {
0075 cpu = <&A57_0>;
0076 };
0077 core1 {
0078 cpu = <&A57_1>;
0079 };
0080 };
0081
0082 cluster1 {
0083 core0 {
0084 cpu = <&A53_0>;
0085 };
0086 core1 {
0087 cpu = <&A53_1>;
0088 };
0089 core2 {
0090 cpu = <&A53_2>;
0091 };
0092 core3 {
0093 cpu = <&A53_3>;
0094 };
0095 };
0096 };
0097
0098 idle-states {
0099 entry-method = "psci";
0100
0101 CPU_SLEEP_0: cpu-sleep-0 {
0102 compatible = "arm,idle-state";
0103 arm,psci-suspend-param = <0x0010000>;
0104 local-timer-stop;
0105 entry-latency-us = <100>;
0106 exit-latency-us = <250>;
0107 min-residency-us = <150>;
0108 };
0109
0110 CLUSTER_SLEEP_0: cluster-sleep-0 {
0111 compatible = "arm,idle-state";
0112 arm,psci-suspend-param = <0x1010000>;
0113 local-timer-stop;
0114 entry-latency-us = <800>;
0115 exit-latency-us = <700>;
0116 min-residency-us = <2500>;
0117 };
0118 };
0119
0120 A57_0: cpu@0 {
0121 compatible = "arm,cortex-a57";
0122 reg = <0x0 0x0>;
0123 device_type = "cpu";
0124 enable-method = "psci";
0125 next-level-cache = <&A57_L2>;
0126 clocks = <&scpi_dvfs 0>;
0127 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0128 capacity-dmips-mhz = <1024>;
0129 };
0130
0131 A57_1: cpu@1 {
0132 compatible = "arm,cortex-a57";
0133 reg = <0x0 0x1>;
0134 device_type = "cpu";
0135 enable-method = "psci";
0136 next-level-cache = <&A57_L2>;
0137 clocks = <&scpi_dvfs 0>;
0138 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0139 capacity-dmips-mhz = <1024>;
0140 };
0141
0142 A53_0: cpu@100 {
0143 compatible = "arm,cortex-a53";
0144 reg = <0x0 0x100>;
0145 device_type = "cpu";
0146 enable-method = "psci";
0147 next-level-cache = <&A53_L2>;
0148 clocks = <&scpi_dvfs 1>;
0149 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0150 capacity-dmips-mhz = <578>;
0151 };
0152
0153 A53_1: cpu@101 {
0154 compatible = "arm,cortex-a53";
0155 reg = <0x0 0x101>;
0156 device_type = "cpu";
0157 enable-method = "psci";
0158 next-level-cache = <&A53_L2>;
0159 clocks = <&scpi_dvfs 1>;
0160 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0161 capacity-dmips-mhz = <578>;
0162 };
0163
0164 A53_2: cpu@102 {
0165 compatible = "arm,cortex-a53";
0166 reg = <0x0 0x102>;
0167 device_type = "cpu";
0168 enable-method = "psci";
0169 next-level-cache = <&A53_L2>;
0170 clocks = <&scpi_dvfs 1>;
0171 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0172 capacity-dmips-mhz = <578>;
0173 };
0174
0175 A53_3: cpu@103 {
0176 compatible = "arm,cortex-a53";
0177 reg = <0x0 0x103>;
0178 device_type = "cpu";
0179 enable-method = "psci";
0180 next-level-cache = <&A53_L2>;
0181 clocks = <&scpi_dvfs 1>;
0182 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0183 capacity-dmips-mhz = <578>;
0184 };
0185
0186 A57_L2: l2-cache0 {
0187 compatible = "cache";
0188 };
0189
0190 A53_L2: l2-cache1 {
0191 compatible = "cache";
0192 };
0193 };
0194
0195 Example 2 (ARM 32-bit, 4-cpu system, two clusters,
0196 cpus 0,1@1GHz, cpus 2,3@500MHz):
0197 capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first
0198 cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency)
0199
0200 cpus {
0201 #address-cells = <1>;
0202 #size-cells = <0>;
0203
0204 cpu0: cpu@0 {
0205 device_type = "cpu";
0206 compatible = "arm,cortex-a15";
0207 reg = <0>;
0208 capacity-dmips-mhz = <2>;
0209 };
0210
0211 cpu1: cpu@1 {
0212 device_type = "cpu";
0213 compatible = "arm,cortex-a15";
0214 reg = <1>;
0215 capacity-dmips-mhz = <2>;
0216 };
0217
0218 cpu2: cpu@2 {
0219 device_type = "cpu";
0220 compatible = "arm,cortex-a15";
0221 reg = <0x100>;
0222 capacity-dmips-mhz = <1>;
0223 };
0224
0225 cpu3: cpu@3 {
0226 device_type = "cpu";
0227 compatible = "arm,cortex-a15";
0228 reg = <0x101>;
0229 capacity-dmips-mhz = <1>;
0230 };
0231 };
0232
0233 ===========================================
0234 5 - References
0235 ===========================================
0236
0237 [1] ARM Linux Kernel documentation - CPUs bindings
0238 Documentation/devicetree/bindings/arm/cpus.yaml
