0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: CCI Interconnect Bus Masters binding
0008
0009 maintainers:
0010 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
0011
0012 description: |
0013 Masters in the device tree connected to a CCI port (inclusive of CPUs
0014 and their cpu nodes).
0015
0016 select: true
0017
0018 properties:
0019 cci-control-port:
0020 $ref: /schemas/types.yaml#/definitions/phandle
0021
0022 additionalProperties: true
0023
0024 examples:
0025 - |
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029
0030 cpu@0 {
0031 compatible = "arm,cortex-a15";
0032 device_type = "cpu";
0033 cci-control-port = <&cci_control1>;
0034 reg = <0>;
0035 };
0036 };
0037
0038 ...
