0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Calxeda Highbank L2 cache ECC
0008
0009 description: |
0010 Binding for the Calxeda Highbank L2 cache controller ECC device.
0011 This does not cover the actual L2 cache controller control registers,
0012 but just the error reporting functionality.
0013
0014 maintainers:
0015 - Andre Przywara <andre.przywara@arm.com>
0016
0017 properties:
0018 compatible:
0019 const: "calxeda,hb-sregs-l2-ecc"
0020
0021 reg:
0022 maxItems: 1
0023
0024 interrupts:
0025 items:
0026 - description: single bit error interrupt
0027 - description: double bit error interrupt
0028
0029 required:
0030 - compatible
0031 - reg
0032 - interrupts
0033
0034 additionalProperties: false
0035
0036 examples:
0037 - |
0038 sregs@fff3c200 {
0039 compatible = "calxeda,hb-sregs-l2-ecc";
0040 reg = <0xfff3c200 0x100>;
0041 interrupts = <0 71 4>, <0 72 4>;
0042 };
