0001 ARM Broadcom STB platforms Device Tree Bindings
0002 -----------------------------------------------
0003 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
0004 SoC shall have the following DT organization:
0005
0006 Required root node properties:
0007 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
0008
0009 example:
0010 / {
0011 #address-cells = <2>;
0012 #size-cells = <2>;
0013 model = "Broadcom STB (bcm7445)";
0014 compatible = "brcm,bcm7445", "brcm,brcmstb";
0015
0016 Further, syscon nodes that map platform-specific registers used for general
0017 system control is required:
0018
0019 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
0020 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
0021 "brcm,brcmstb-cpu-biu-ctrl",
0022 "syscon"
0023 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
0024
0025 cpu-biu-ctrl node
0026 -------------------
0027 SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
0028 specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
0029 complex to the different Memory Controller Ports (MCP), one per memory
0030 controller (MEMC). This BIU block offers a feature called Write Pairing which
0031 consists in collapsing two adjacent cache lines into a single (bursted) write
0032 transaction towards the memory controller (MEMC) to maximize write bandwidth.
0033
0034 Required properties:
0035
0036 - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"
0037
0038 Optional properties:
0039
0040 - brcm,write-pairing:
0041 Boolean property, which when present indicates that the chip
0042 supports write-pairing.
0043
0044 example:
0045 rdb {
0046 #address-cells = <1>;
0047 #size-cells = <1>;
0048 compatible = "simple-bus";
0049 ranges = <0 0x00 0xf0000000 0x1000000>;
0050
0051 sun_top_ctrl: syscon@404000 {
0052 compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
0053 reg = <0x404000 0x51c>;
0054 };
0055
0056 hif_cpubiuctrl: syscon@3e2400 {
0057 compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
0058 reg = <0x3e2400 0x5b4>;
0059 brcm,write-pairing;
0060 };
0061
0062 hif_continuation: syscon@452000 {
0063 compatible = "brcm,bcm7445-hif-continuation", "syscon";
0064 reg = <0x452000 0x100>;
0065 };
0066 };
0067
0068 Nodes that allow for support of SMP initialization and reboot are required:
0069
0070 smpboot
0071 -------
0072 Required properties:
0073
0074 - compatible
0075 The string "brcm,brcmstb-smpboot".
0076
0077 - syscon-cpu
0078 A phandle / integer array property which lets the BSP know the location
0079 of certain CPU power-on registers.
0080
0081 The layout of the property is as follows:
0082 o a phandle to the "hif_cpubiuctrl" syscon node
0083 o offset to the base CPU power zone register
0084 o offset to the base CPU reset register
0085
0086 - syscon-cont
0087 A phandle pointing to the syscon node which describes the CPU boot
0088 continuation registers.
0089 o a phandle to the "hif_continuation" syscon node
0090
0091 example:
0092 smpboot {
0093 compatible = "brcm,brcmstb-smpboot";
0094 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
0095 syscon-cont = <&hif_continuation>;
0096 };
0097
0098 reboot
0099 -------
0100 Required properties
0101
0102 - compatible
0103 The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with
0104 the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm
0105 chips with the old SUN_TOP_CTRL interface.
0106
0107 - syscon
0108 A phandle / integer array that points to the syscon node which describes
0109 the general system reset registers.
0110 o a phandle to "sun_top_ctrl"
0111 o offset to the "reset source enable" register
0112 o offset to the "software master reset" register
0113
0114 example:
0115 reboot {
0116 compatible = "brcm,brcmstb-reboot";
0117 syscon = <&sun_top_ctrl 0x304 0x308>;
0118 };
0119
0120
0121
0122 Power management
0123 ----------------
0124
0125 For power management (particularly, S2/S3/S5 system suspend), the following SoC
0126 components are needed:
0127
0128 = Always-On control block (AON CTRL)
0129
0130 This hardware provides control registers for the "always-on" (even in low-power
0131 modes) hardware, such as the Power Management State Machine (PMSM).
0132
0133 Required properties:
0134 - compatible : should contain "brcm,brcmstb-aon-ctrl"
0135 - reg : the register start and length for the AON CTRL block
0136
0137 Example:
0138
0139 aon-ctrl@410000 {
0140 compatible = "brcm,brcmstb-aon-ctrl";
0141 reg = <0x410000 0x400>;
0142 };
0143
0144 = Memory controllers
0145
0146 A Broadcom STB SoC typically has a number of independent memory controllers,
0147 each of which may have several associated hardware blocks, which are versioned
0148 independently (control registers, DDR PHYs, etc.). One might consider
0149 describing these controllers as a parent "memory controllers" block, which
0150 contains N sub-nodes (one for each controller in the system), each of which is
0151 associated with a number of hardware register resources (e.g., its PHY). See
0152 the example device tree snippet below.
0153
0154 == MEMC (MEMory Controller)
0155
0156 Represents a single memory controller instance.
0157
0158 Required properties:
0159 - compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
0160
0161 Should contain subnodes for any of the following relevant hardware resources:
0162
0163 == DDR PHY control
0164
0165 Control registers for this memory controller's DDR PHY.
0166
0167 Required properties:
0168 - compatible : should contain one of these
0169 "brcm,brcmstb-ddr-phy-v71.1"
0170 "brcm,brcmstb-ddr-phy-v72.0"
0171 "brcm,brcmstb-ddr-phy-v225.1"
0172 "brcm,brcmstb-ddr-phy-v240.1"
0173 "brcm,brcmstb-ddr-phy-v240.2"
0174
0175 - reg : the DDR PHY register range
0176
0177 == DDR SHIMPHY
0178
0179 Control registers for this memory controller's DDR SHIMPHY.
0180
0181 Required properties:
0182 - compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
0183 - reg : the DDR SHIMPHY register range
0184
0185 == MEMC DDR control
0186
0187 Sequencer DRAM parameters and control registers. Used for Self-Refresh
0188 Power-Down (SRPD), among other things.
0189
0190 Required properties:
0191 - compatible : should contain one of these
0192 "brcm,brcmstb-memc-ddr-rev-b.2.1"
0193 "brcm,brcmstb-memc-ddr-rev-b.2.2"
0194 "brcm,brcmstb-memc-ddr-rev-b.2.3"
0195 "brcm,brcmstb-memc-ddr-rev-b.3.0"
0196 "brcm,brcmstb-memc-ddr-rev-b.3.1"
0197 "brcm,brcmstb-memc-ddr"
0198 - reg : the MEMC DDR register range
0199
0200 Example:
0201
0202 memory_controllers {
0203 ranges;
0204 compatible = "simple-bus";
0205
0206 memc@0 {
0207 compatible = "brcm,brcmstb-memc", "simple-bus";
0208 ranges;
0209
0210 ddr-phy@f1106000 {
0211 compatible = "brcm,brcmstb-ddr-phy-v240.1";
0212 reg = <0xf1106000 0x21c>;
0213 };
0214
0215 shimphy@f1108000 {
0216 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
0217 reg = <0xf1108000 0xe4>;
0218 };
0219
0220 memc-ddr@f1102000 {
0221 reg = <0xf1102000 0x800>;
0222 compatible = "brcm,brcmstb-memc-ddr";
0223 };
0224 };
0225
0226 memc@1 {
0227 compatible = "brcm,brcmstb-memc", "simple-bus";
0228 ranges;
0229
0230 ddr-phy@f1186000 {
0231 compatible = "brcm,brcmstb-ddr-phy-v240.1";
0232 reg = <0xf1186000 0x21c>;
0233 };
0234
0235 shimphy@f1188000 {
0236 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
0237 reg = <0xf1188000 0xe4>;
0238 };
0239
0240 memc-ddr@f1182000 {
0241 reg = <0xf1182000 0x800>;
0242 compatible = "brcm,brcmstb-memc-ddr";
0243 };
0244 };
0245
0246 memc@2 {
0247 compatible = "brcm,brcmstb-memc", "simple-bus";
0248 ranges;
0249
0250 ddr-phy@f1206000 {
0251 compatible = "brcm,brcmstb-ddr-phy-v240.1";
0252 reg = <0xf1206000 0x21c>;
0253 };
0254
0255 shimphy@f1208000 {
0256 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
0257 reg = <0xf1208000 0xe4>;
0258 };
0259
0260 memc-ddr@f1202000 {
0261 reg = <0xf1202000 0x800>;
0262 compatible = "brcm,brcmstb-memc-ddr";
0263 };
0264 };
0265 };
