0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Arm CoreSight Trace Memory Controller
0008
0009 maintainers:
0010 - Mathieu Poirier <mathieu.poirier@linaro.org>
0011 - Mike Leach <mike.leach@linaro.org>
0012 - Leo Yan <leo.yan@linaro.org>
0013 - Suzuki K Poulose <suzuki.poulose@arm.com>
0014
0015 description: |
0016 CoreSight components are compliant with the ARM CoreSight architecture
0017 specification and can be connected in various topologies to suit a particular
0018 SoCs tracing needs. These trace components can generally be classified as
0019 sinks, links and sources. Trace data produced by one or more sources flows
0020 through the intermediate links connecting the source to the currently selected
0021 sink.
0022
0023 Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
0024 FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
0025 mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
0026
0027 # Need a custom select here or 'arm,primecell' will match on lots of nodes
0028 select:
0029 properties:
0030 compatible:
0031 contains:
0032 const: arm,coresight-tmc
0033 required:
0034 - compatible
0035
0036 allOf:
0037 - $ref: /schemas/arm/primecell.yaml#
0038
0039 properties:
0040 compatible:
0041 items:
0042 - const: arm,coresight-tmc
0043 - const: arm,primecell
0044
0045 reg:
0046 maxItems: 1
0047
0048 clocks:
0049 minItems: 1
0050 maxItems: 2
0051
0052 clock-names:
0053 minItems: 1
0054 items:
0055 - const: apb_pclk
0056 - const: atclk
0057
0058 arm,buffer-size:
0059 $ref: /schemas/types.yaml#/definitions/uint32
0060 deprecated: true
0061 description:
0062 Size of contiguous buffer space for TMC ETR (embedded trace router). The
0063 buffer size can be configured dynamically via buffer_size property in
0064 sysfs instead.
0065
0066 arm,scatter-gather:
0067 type: boolean
0068 description:
0069 Indicates that the TMC-ETR can safely use the SG mode on this system.
0070
0071 arm,max-burst-size:
0072 description:
0073 The maximum burst size initiated by TMC on the AXI master interface. The
0074 burst size can be in the range [0..15], the setting supports one data
0075 transfer per burst up to a maximum of 16 data transfers per burst.
0076 $ref: /schemas/types.yaml#/definitions/uint32
0077 maximum: 15
0078
0079 in-ports:
0080 $ref: /schemas/graph.yaml#/properties/ports
0081 additionalProperties: false
0082
0083 properties:
0084 port:
0085 description: Input connection from the CoreSight Trace bus.
0086 $ref: /schemas/graph.yaml#/properties/port
0087
0088 out-ports:
0089 $ref: /schemas/graph.yaml#/properties/ports
0090 additionalProperties: false
0091
0092 properties:
0093 port:
0094 description: AXI or ATB Master output connection. Used for ETR
0095 and ETF configurations.
0096 $ref: /schemas/graph.yaml#/properties/port
0097
0098 required:
0099 - compatible
0100 - reg
0101 - clocks
0102 - clock-names
0103 - in-ports
0104
0105 unevaluatedProperties: false
0106
0107 examples:
0108 - |
0109 etr@20070000 {
0110 compatible = "arm,coresight-tmc", "arm,primecell";
0111 reg = <0x20070000 0x1000>;
0112
0113 clocks = <&oscclk6a>;
0114 clock-names = "apb_pclk";
0115 in-ports {
0116 port {
0117 etr_in_port: endpoint {
0118 remote-endpoint = <&replicator2_out_port0>;
0119 };
0120 };
0121 };
0122
0123 out-ports {
0124 port {
0125 etr_out_port: endpoint {
0126 remote-endpoint = <&catu_in_port>;
0127 };
0128 };
0129 };
0130 };
0131 ...
