0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Arm CoreSight System Trace MacroCell
0008
0009 maintainers:
0010 - Mathieu Poirier <mathieu.poirier@linaro.org>
0011 - Mike Leach <mike.leach@linaro.org>
0012 - Leo Yan <leo.yan@linaro.org>
0013 - Suzuki K Poulose <suzuki.poulose@arm.com>
0014
0015 description: |
0016 CoreSight components are compliant with the ARM CoreSight architecture
0017 specification and can be connected in various topologies to suit a particular
0018 SoCs tracing needs. These trace components can generally be classified as
0019 sinks, links and sources. Trace data produced by one or more sources flows
0020 through the intermediate links connecting the source to the currently selected
0021 sink.
0022
0023 The STM is a trace source that is integrated into a CoreSight system, designed
0024 primarily for high-bandwidth trace of instrumentation embedded into software.
0025 This instrumentation is made up of memory-mapped writes to the STM Advanced
0026 eXtensible Interface (AXI) slave, which carry information about the behavior
0027 of the software.
0028
0029 select:
0030 properties:
0031 compatible:
0032 contains:
0033 const: arm,coresight-stm
0034 required:
0035 - compatible
0036
0037 allOf:
0038 - $ref: /schemas/arm/primecell.yaml#
0039
0040 properties:
0041 compatible:
0042 items:
0043 - const: arm,coresight-stm
0044 - const: arm,primecell
0045
0046 reg:
0047 maxItems: 2
0048
0049 reg-names:
0050 items:
0051 - const: stm-base
0052 - const: stm-stimulus-base
0053
0054 clocks:
0055 minItems: 1
0056 maxItems: 2
0057
0058 clock-names:
0059 minItems: 1
0060 items:
0061 - const: apb_pclk
0062 - const: atclk
0063
0064 out-ports:
0065 $ref: /schemas/graph.yaml#/properties/ports
0066 additionalProperties: false
0067
0068 properties:
0069 port:
0070 description: Output connection to the CoreSight Trace bus.
0071 $ref: /schemas/graph.yaml#/properties/port
0072
0073 required:
0074 - compatible
0075 - reg
0076 - reg-names
0077 - clocks
0078 - clock-names
0079 - out-ports
0080
0081 unevaluatedProperties: false
0082
0083 examples:
0084 - |
0085 stm@20100000 {
0086 compatible = "arm,coresight-stm", "arm,primecell";
0087 reg = <0x20100000 0x1000>,
0088 <0x28000000 0x180000>;
0089 reg-names = "stm-base", "stm-stimulus-base";
0090
0091 clocks = <&soc_smc50mhz>;
0092 clock-names = "apb_pclk";
0093 out-ports {
0094 port {
0095 stm_out_port: endpoint {
0096 remote-endpoint = <&main_funnel_in_port2>;
0097 };
0098 };
0099 };
0100 };
0101 ...
