0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Arm CoreSight Embedded Trace MacroCell
0008
0009 maintainers:
0010 - Mathieu Poirier <mathieu.poirier@linaro.org>
0011 - Mike Leach <mike.leach@linaro.org>
0012 - Leo Yan <leo.yan@linaro.org>
0013 - Suzuki K Poulose <suzuki.poulose@arm.com>
0014
0015 description: |
0016 CoreSight components are compliant with the ARM CoreSight architecture
0017 specification and can be connected in various topologies to suit a particular
0018 SoCs tracing needs. These trace components can generally be classified as
0019 sinks, links and sources. Trace data produced by one or more sources flows
0020 through the intermediate links connecting the source to the currently selected
0021 sink.
0022
0023 The Embedded Trace Macrocell (ETM) is a real-time trace module providing
0024 instruction and data tracing of a processor.
0025
0026 select:
0027 properties:
0028 compatible:
0029 contains:
0030 enum:
0031 - arm,coresight-etm3x
0032 - arm,coresight-etm4x
0033 - arm,coresight-etm4x-sysreg
0034 required:
0035 - compatible
0036
0037 allOf:
0038 - if:
0039 not:
0040 properties:
0041 compatible:
0042 contains:
0043 const: arm,coresight-etm4x-sysreg
0044 then:
0045 $ref: /schemas/arm/primecell.yaml#
0046 required:
0047 - reg
0048
0049 properties:
0050 compatible:
0051 oneOf:
0052 - description:
0053 Embedded Trace Macrocell with memory mapped access.
0054 items:
0055 - enum:
0056 - arm,coresight-etm3x
0057 - arm,coresight-etm4x
0058 - const: arm,primecell
0059 - description:
0060 Embedded Trace Macrocell (version 4.x), with system register access only
0061 const: arm,coresight-etm4x-sysreg
0062
0063 reg:
0064 maxItems: 1
0065
0066 clocks:
0067 minItems: 1
0068 maxItems: 2
0069
0070 clock-names:
0071 minItems: 1
0072 items:
0073 - const: apb_pclk
0074 - const: atclk
0075
0076 arm,coresight-loses-context-with-cpu:
0077 type: boolean
0078 description:
0079 Indicates that the hardware will lose register context on CPU power down
0080 (e.g. CPUIdle). An example of where this may be needed are systems which
0081 contain a coresight component and CPU in the same power domain. When the
0082 CPU powers down the coresight component also powers down and loses its
0083 context.
0084
0085 arm,cp14:
0086 type: boolean
0087 description:
0088 Must be present if the system accesses ETM/PTM management registers via
0089 co-processor 14.
0090
0091 qcom,skip-power-up:
0092 type: boolean
0093 description:
0094 Indicates that an implementation can skip powering up the trace unit.
0095 TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
0096 since ETMs are in the same power domain as their CPU cores. This property
0097 is required to identify such systems with hardware errata where the CPU
0098 watchdog counter is stopped when TRCPDCR.PU is set.
0099
0100 cpu:
0101 description:
0102 phandle to the cpu this ETM is bound to.
0103 $ref: /schemas/types.yaml#/definitions/phandle
0104
0105 out-ports:
0106 $ref: /schemas/graph.yaml#/properties/ports
0107 additionalProperties: false
0108
0109 properties:
0110 port:
0111 description: Output connection from the ETM to CoreSight Trace bus.
0112 $ref: /schemas/graph.yaml#/properties/port
0113
0114 required:
0115 - compatible
0116 - clocks
0117 - clock-names
0118 - cpu
0119 - out-ports
0120
0121 unevaluatedProperties: false
0122
0123 examples:
0124 - |
0125 ptm@2201c000 {
0126 compatible = "arm,coresight-etm3x", "arm,primecell";
0127 reg = <0x2201c000 0x1000>;
0128
0129 cpu = <&cpu0>;
0130 clocks = <&oscclk6a>;
0131 clock-names = "apb_pclk";
0132 out-ports {
0133 port {
0134 ptm0_out_port: endpoint {
0135 remote-endpoint = <&funnel_in_port0>;
0136 };
0137 };
0138 };
0139 };
0140
0141 ptm@2201d000 {
0142 compatible = "arm,coresight-etm3x", "arm,primecell";
0143 reg = <0x2201d000 0x1000>;
0144
0145 cpu = <&cpu1>;
0146 clocks = <&oscclk6a>;
0147 clock-names = "apb_pclk";
0148 out-ports {
0149 port {
0150 ptm1_out_port: endpoint {
0151 remote-endpoint = <&funnel_in_port1>;
0152 };
0153 };
0154 };
0155 };
0156 ...
