0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 # Copyright 2019 Linaro Ltd.
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: ARM Coresight Cross Trigger Interface (CTI) device.
0009
0010 description: |
0011 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
0012 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
0013 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
0014 The ECT components are not part of the trace generation data path and are thus
0015 not part of the CoreSight graph.
0016
0017 The CTI component properties define the connections between the individual
0018 CTI and the components it is directly connected to, consisting of input and
0019 output hardware trigger signals. CTIs can have a maximum number of input and
0020 output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
0021 number is defined at design time, the maximum of each defined in the DEVID
0022 register.
0023
0024 CTIs are interconnected in a star topology via the CTM, using a number of
0025 programmable channels, usually 4, but again implementation defined and
0026 described in the DEVID register. The star topology is not required to be
0027 described in the bindings as the actual connections are software
0028 programmable.
0029
0030 In general the connections between CTI and components via the trigger signals
0031 are implementation defined, except when the CTI is connected to an ARM v8
0032 architecture core and optional ETM.
0033
0034 In this case the ARM v8 architecture defines the required signal connections
0035 between CTI and the CPU core and ETM if present. In the case of a v8
0036 architecturally connected CTI an additional compatible string is used to
0037 indicate this feature (arm,coresight-cti-v8-arch).
0038
0039 When CTI trigger connection information is unavailable then a minimal driver
0040 binding can be declared with no explicit trigger signals. This will result
0041 the driver detecting the maximum available triggers and channels from the
0042 DEVID register and make them all available for use as a single default
0043 connection. Any user / client application will require additional information
0044 on the connections between the CTI and other components for correct operation.
0045 This information might be found by enabling the Integration Test registers in
0046 the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel
0047 configuration). These registers may be used to explore the trigger connections
0048 between CTI and other CoreSight components.
0049
0050 Certain triggers between CoreSight devices and the CTI have specific types
0051 and usages. These can be defined along with the signal indexes with the
0052 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
0053
0054 For example a CTI connected to a core will usually have a DBGREQ signal. This
0055 is defined in the binding as type PE_EDBGREQ. These types will appear in an
0056 optional array alongside the signal indexes. Omitting types will default all
0057 signals to GEN_IO.
0058
0059 Note that some hardware trigger signals can be connected to non-CoreSight
0060 components (e.g. UART etc) depending on hardware implementation.
0061
0062 maintainers:
0063 - Mike Leach <mike.leach@linaro.org>
0064
0065 allOf:
0066 - $ref: /schemas/arm/primecell.yaml#
0067
0068 # Need a custom select here or 'arm,primecell' will match on lots of nodes
0069 select:
0070 properties:
0071 compatible:
0072 contains:
0073 enum:
0074 - arm,coresight-cti
0075 required:
0076 - compatible
0077
0078 properties:
0079 $nodename:
0080 pattern: "^cti(@[0-9a-f]+)$"
0081 compatible:
0082 oneOf:
0083 - items:
0084 - const: arm,coresight-cti
0085 - const: arm,primecell
0086 - items:
0087 - const: arm,coresight-cti-v8-arch
0088 - const: arm,coresight-cti
0089 - const: arm,primecell
0090
0091 reg:
0092 maxItems: 1
0093
0094 cpu:
0095 $ref: /schemas/types.yaml#/definitions/phandle
0096 description:
0097 Handle to cpu this device is associated with. This must appear in the
0098 base cti node if compatible string arm,coresight-cti-v8-arch is used,
0099 or may appear in a trig-conns child node when appropriate.
0100
0101 arm,cti-ctm-id:
0102 $ref: /schemas/types.yaml#/definitions/uint32
0103 description:
0104 Defines the CTM this CTI is connected to, in large systems with multiple
0105 separate CTI/CTM nets. Typically multi-socket systems where the CTM is
0106 propagated between sockets.
0107
0108 arm,cs-dev-assoc:
0109 $ref: /schemas/types.yaml#/definitions/phandle
0110 description:
0111 defines a phandle reference to an associated CoreSight trace device.
0112 When the associated trace device is enabled, then the respective CTI
0113 will be enabled. Use in a trig-conns node, or in CTI base node when
0114 compatible string arm,coresight-cti-v8-arch used. If the associated
0115 device has not been registered then the node name will be stored as
0116 the connection name for later resolution. If the associated device is
0117 not a CoreSight device or not registered then the node name will remain
0118 the connection name and automatic enabling will not occur.
0119
0120 # size cells and address cells required if trig-conns node present.
0121 "#size-cells":
0122 const: 0
0123
0124 "#address-cells":
0125 const: 1
0126
0127 patternProperties:
0128 '^trig-conns@([0-9]+)$':
0129 type: object
0130 description:
0131 A trigger connections child node which describes the trigger signals
0132 between this CTI and another hardware device. This device may be a CPU,
0133 CoreSight device, any other hardware device or simple external IO lines.
0134 The connection may have both input and output triggers, or only one or the
0135 other.
0136
0137 properties:
0138 reg:
0139 maxItems: 1
0140
0141 arm,trig-in-sigs:
0142 $ref: /schemas/types.yaml#/definitions/uint32-array
0143 minItems: 1
0144 maxItems: 32
0145 description:
0146 List of CTI trigger in signal numbers in use by a trig-conns node.
0147
0148 arm,trig-in-types:
0149 $ref: /schemas/types.yaml#/definitions/uint32-array
0150 minItems: 1
0151 maxItems: 32
0152 description:
0153 List of constants representing the types for the CTI trigger in
0154 signals. Types in this array match to the corresponding signal in the
0155 arm,trig-in-sigs array. If the -types array is smaller, or omitted
0156 completely, then the types will default to GEN_IO.
0157
0158 arm,trig-out-sigs:
0159 $ref: /schemas/types.yaml#/definitions/uint32-array
0160 minItems: 1
0161 maxItems: 32
0162 description:
0163 List of CTI trigger out signal numbers in use by a trig-conns node.
0164
0165 arm,trig-out-types:
0166 $ref: /schemas/types.yaml#/definitions/uint32-array
0167 minItems: 1
0168 maxItems: 32
0169 description:
0170 List of constants representing the types for the CTI trigger out
0171 signals. Types in this array match to the corresponding signal
0172 in the arm,trig-out-sigs array. If the "-types" array is smaller,
0173 or omitted completely, then the types will default to GEN_IO.
0174
0175 arm,trig-filters:
0176 $ref: /schemas/types.yaml#/definitions/uint32-array
0177 minItems: 1
0178 maxItems: 32
0179 description:
0180 List of CTI trigger out signals that will be blocked from becoming
0181 active, unless filtering is disabled on the driver.
0182
0183 arm,trig-conn-name:
0184 $ref: /schemas/types.yaml#/definitions/string
0185 description:
0186 Defines a connection name that will be displayed, if the cpu or
0187 arm,cs-dev-assoc properties are not being used in this connection.
0188 Principle use for CTI that are connected to non-CoreSight devices, or
0189 external IO.
0190
0191 anyOf:
0192 - required:
0193 - arm,trig-in-sigs
0194 - required:
0195 - arm,trig-out-sigs
0196 oneOf:
0197 - required:
0198 - arm,trig-conn-name
0199 - required:
0200 - cpu
0201 - required:
0202 - arm,cs-dev-assoc
0203 required:
0204 - reg
0205
0206 required:
0207 - compatible
0208 - reg
0209 - clocks
0210 - clock-names
0211
0212 if:
0213 properties:
0214 compatible:
0215 contains:
0216 const: arm,coresight-cti-v8-arch
0217
0218 then:
0219 required:
0220 - cpu
0221
0222 unevaluatedProperties: false
0223
0224 examples:
0225 # minimum CTI definition. DEVID register used to set number of triggers.
0226 - |
0227 cti@20020000 {
0228 compatible = "arm,coresight-cti", "arm,primecell";
0229 reg = <0x20020000 0x1000>;
0230
0231 clocks = <&soc_smc50mhz>;
0232 clock-names = "apb_pclk";
0233 };
0234 # v8 architecturally defined CTI - CPU + ETM connections generated by the
0235 # driver according to the v8 architecture specification.
0236 - |
0237 cti@859000 {
0238 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
0239 "arm,primecell";
0240 reg = <0x859000 0x1000>;
0241
0242 clocks = <&soc_smc50mhz>;
0243 clock-names = "apb_pclk";
0244
0245 cpu = <&CPU1>;
0246 arm,cs-dev-assoc = <&etm1>;
0247 };
0248 # Implementation defined CTI - CPU + ETM connections explicitly defined..
0249 # Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h
0250 # #size-cells and #address-cells are required if trig-conns@ nodes present.
0251 - |
0252 #include <dt-bindings/arm/coresight-cti-dt.h>
0253
0254 cti@858000 {
0255 compatible = "arm,coresight-cti", "arm,primecell";
0256 reg = <0x858000 0x1000>;
0257
0258 clocks = <&soc_smc50mhz>;
0259 clock-names = "apb_pclk";
0260
0261 arm,cti-ctm-id = <1>;
0262
0263 #address-cells = <1>;
0264 #size-cells = <0>;
0265
0266 trig-conns@0 {
0267 reg = <0>;
0268 arm,trig-in-sigs = <4 5 6 7>;
0269 arm,trig-in-types = <ETM_EXTOUT
0270 ETM_EXTOUT
0271 ETM_EXTOUT
0272 ETM_EXTOUT>;
0273 arm,trig-out-sigs = <4 5 6 7>;
0274 arm,trig-out-types = <ETM_EXTIN
0275 ETM_EXTIN
0276 ETM_EXTIN
0277 ETM_EXTIN>;
0278 arm,cs-dev-assoc = <&etm0>;
0279 };
0280
0281 trig-conns@1 {
0282 reg = <1>;
0283 cpu = <&CPU0>;
0284 arm,trig-in-sigs = <0 1>;
0285 arm,trig-in-types = <PE_DBGTRIGGER
0286 PE_PMUIRQ>;
0287 arm,trig-out-sigs=<0 1 2 >;
0288 arm,trig-out-types = <PE_EDBGREQ
0289 PE_DBGRESTART
0290 PE_CTIIRQ>;
0291
0292 arm,trig-filters = <0>;
0293 };
0294 };
0295 # Implementation defined CTI - non CoreSight component connections.
0296 - |
0297 cti@20110000 {
0298 compatible = "arm,coresight-cti", "arm,primecell";
0299 reg = <0x20110000 0x1000>;
0300
0301 clocks = <&soc_smc50mhz>;
0302 clock-names = "apb_pclk";
0303
0304 #address-cells = <1>;
0305 #size-cells = <0>;
0306
0307 trig-conns@0 {
0308 reg = <0>;
0309 arm,trig-in-sigs=<0>;
0310 arm,trig-in-types=<GEN_INTREQ>;
0311 arm,trig-out-sigs=<0>;
0312 arm,trig-out-types=<GEN_HALTREQ>;
0313 arm,trig-conn-name = "sys_profiler";
0314 };
0315
0316 trig-conns@1 {
0317 reg = <1>;
0318 arm,trig-out-sigs=<2 3>;
0319 arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
0320 arm,trig-conn-name = "watchdog";
0321 };
0322
0323 trig-conns@2 {
0324 reg = <2>;
0325 arm,trig-in-sigs=<1 6>;
0326 arm,trig-in-types=<GEN_HALTREQ GEN_RESTARTREQ>;
0327 arm,trig-conn-name = "g_counter";
0328 };
0329 };
0330
0331 ...
