0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Arm Coresight Address Translation Unit (CATU)
0008
0009 maintainers:
0010 - Mathieu Poirier <mathieu.poirier@linaro.org>
0011 - Mike Leach <mike.leach@linaro.org>
0012 - Leo Yan <leo.yan@linaro.org>
0013 - Suzuki K Poulose <suzuki.poulose@arm.com>
0014
0015 description: |
0016 CoreSight components are compliant with the ARM CoreSight architecture
0017 specification and can be connected in various topologies to suit a particular
0018 SoCs tracing needs. These trace components can generally be classified as
0019 sinks, links and sources. Trace data produced by one or more sources flows
0020 through the intermediate links connecting the source to the currently selected
0021 sink.
0022
0023 The CoreSight Address Translation Unit (CATU) translates addresses between an
0024 AXI master and system memory. The CATU is normally used along with the TMC to
0025 implement scattering of virtual trace buffers in physical memory. The CATU
0026 translates contiguous Virtual Addresses (VAs) from an AXI master into
0027 non-contiguous Physical Addresses (PAs) that are intended for system memory.
0028
0029 # Need a custom select here or 'arm,primecell' will match on lots of nodes
0030 select:
0031 properties:
0032 compatible:
0033 contains:
0034 const: arm,coresight-catu
0035 required:
0036 - compatible
0037
0038 allOf:
0039 - $ref: /schemas/arm/primecell.yaml#
0040
0041 properties:
0042 compatible:
0043 items:
0044 - const: arm,coresight-catu
0045 - const: arm,primecell
0046
0047 reg:
0048 maxItems: 1
0049
0050 clocks:
0051 minItems: 1
0052 maxItems: 2
0053
0054 clock-names:
0055 minItems: 1
0056 items:
0057 - const: apb_pclk
0058 - const: atclk
0059
0060 interrupts:
0061 maxItems: 1
0062 description: Address translation error interrupt
0063
0064 in-ports:
0065 $ref: /schemas/graph.yaml#/properties/ports
0066 additionalProperties: false
0067
0068 properties:
0069 port:
0070 description: AXI Slave connected to another Coresight component
0071 $ref: /schemas/graph.yaml#/properties/port
0072
0073 required:
0074 - compatible
0075 - reg
0076 - clocks
0077 - clock-names
0078 - in-ports
0079
0080 unevaluatedProperties: false
0081
0082 examples:
0083 - |
0084 #include <dt-bindings/interrupt-controller/arm-gic.h>
0085 catu@207e0000 {
0086 compatible = "arm,coresight-catu", "arm,primecell";
0087 reg = <0x207e0000 0x1000>;
0088
0089 clocks = <&oscclk6a>;
0090 clock-names = "apb_pclk";
0091
0092 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0093 in-ports {
0094 port {
0095 catu_in_port: endpoint {
0096 remote-endpoint = <&etr_out_port>;
0097 };
0098 };
0099 };
0100 };
0101 ...
