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0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: ARM CCI Cache Coherent Interconnect Device Tree Binding
0008 
0009 maintainers:
0010   - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
0011 
0012 description: >
0013   ARM multi-cluster systems maintain intra-cluster coherency through a cache
0014   coherent interconnect (CCI) that is capable of monitoring bus transactions
0015   and manage coherency, TLB invalidations and memory barriers.
0016 
0017   It allows snooping and distributed virtual memory message broadcast across
0018   clusters, through memory mapped interface, with a global control register
0019   space and multiple sets of interface control registers, one per slave
0020   interface.
0021 
0022 properties:
0023   $nodename:
0024     pattern: "^cci(@[0-9a-f]+)?$"
0025 
0026   compatible:
0027     enum:
0028       - arm,cci-400
0029       - arm,cci-500
0030       - arm,cci-550
0031 
0032   reg:
0033     maxItems: 1
0034     description: >
0035       Specifies base physical address of CCI control registers common to all
0036       interfaces.
0037 
0038   "#address-cells": true
0039   "#size-cells": true
0040   ranges: true
0041 
0042 patternProperties:
0043   "^slave-if@[0-9a-f]+$":
0044     type: object
0045 
0046     properties:
0047       compatible:
0048         const: arm,cci-400-ctrl-if
0049 
0050       interface-type:
0051         enum:
0052           - ace
0053           - ace-lite
0054 
0055       reg:
0056         maxItems: 1
0057 
0058     required:
0059       - compatible
0060       - interface-type
0061       - reg
0062 
0063     additionalProperties: false
0064 
0065   "^pmu@[0-9a-f]+$":
0066     type: object
0067 
0068     properties:
0069       compatible:
0070         oneOf:
0071           - const: arm,cci-400-pmu,r0
0072           - const: arm,cci-400-pmu,r1
0073           - const: arm,cci-400-pmu
0074             deprecated: true
0075             description: >
0076               Permitted only where OS has secure access to CCI registers
0077           - const: arm,cci-500-pmu,r0
0078           - const: arm,cci-550-pmu,r0
0079 
0080       interrupts:
0081         minItems: 1
0082         maxItems: 8
0083         description: >
0084           List of counter overflow interrupts, one per counter. The interrupts
0085           must be specified starting with the cycle counter overflow interrupt,
0086           followed by counter0 overflow interrupt, counter1 overflow
0087           interrupt,...  ,counterN overflow interrupt.
0088 
0089           The CCI PMU has an interrupt signal for each counter. The number of
0090           interrupts must be equal to the number of counters.
0091 
0092       reg:
0093         maxItems: 1
0094 
0095     required:
0096       - compatible
0097       - interrupts
0098       - reg
0099 
0100     additionalProperties: false
0101 
0102 required:
0103   - "#address-cells"
0104   - "#size-cells"
0105   - compatible
0106   - ranges
0107   - reg
0108 
0109 additionalProperties: false
0110 
0111 examples:
0112   - |
0113       / {
0114           #address-cells = <2>;
0115           #size-cells = <2>;
0116 
0117           compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
0118           model = "V2P-CA15_CA7";
0119           arm,hbi = <0x249>;
0120           interrupt-parent = <&gic>;
0121 
0122           gic: interrupt-controller {
0123               interrupt-controller;
0124               #interrupt-cells = <3>;
0125           };
0126 
0127           /*
0128            * This CCI node corresponds to a CCI component whose control
0129            * registers sits at address 0x000000002c090000.
0130            *
0131            * CCI slave interface @0x000000002c091000 is connected to dma
0132            * controller dma0.
0133            *
0134            * CCI slave interface @0x000000002c094000 is connected to CPUs
0135            * {CPU0, CPU1};
0136            *
0137            * CCI slave interface @0x000000002c095000 is connected to CPUs
0138            * {CPU2, CPU3};
0139            */
0140 
0141           cpus {
0142               #size-cells = <0>;
0143               #address-cells = <1>;
0144 
0145               CPU0: cpu@0 {
0146                   device_type = "cpu";
0147                   compatible = "arm,cortex-a15";
0148                   cci-control-port = <&cci_control1>;
0149                   reg = <0x0>;
0150               };
0151 
0152               CPU1: cpu@1 {
0153                   device_type = "cpu";
0154                   compatible = "arm,cortex-a15";
0155                   cci-control-port = <&cci_control1>;
0156                   reg = <0x1>;
0157               };
0158 
0159               CPU2: cpu@100 {
0160                   device_type = "cpu";
0161                   compatible = "arm,cortex-a7";
0162                   cci-control-port = <&cci_control2>;
0163                   reg = <0x100>;
0164               };
0165 
0166               CPU3: cpu@101 {
0167                   device_type = "cpu";
0168                   compatible = "arm,cortex-a7";
0169                   cci-control-port = <&cci_control2>;
0170                   reg = <0x101>;
0171               };
0172           };
0173 
0174           cci@2c090000 {
0175               compatible = "arm,cci-400";
0176               #address-cells = <1>;
0177               #size-cells = <1>;
0178               reg = <0x0 0x2c090000 0 0x1000>;
0179               ranges = <0x0 0x0 0x2c090000 0x10000>;
0180 
0181               cci_control0: slave-if@1000 {
0182                   compatible = "arm,cci-400-ctrl-if";
0183                   interface-type = "ace-lite";
0184                   reg = <0x1000 0x1000>;
0185               };
0186 
0187               cci_control1: slave-if@4000 {
0188                   compatible = "arm,cci-400-ctrl-if";
0189                   interface-type = "ace";
0190                   reg = <0x4000 0x1000>;
0191               };
0192 
0193               cci_control2: slave-if@5000 {
0194                   compatible = "arm,cci-400-ctrl-if";
0195                   interface-type = "ace";
0196                   reg = <0x5000 0x1000>;
0197               };
0198 
0199               pmu@9000 {
0200                   compatible = "arm,cci-400-pmu";
0201                   reg = <0x9000 0x5000>;
0202                   interrupts = <0 101 4>,
0203                     <0 102 4>,
0204                     <0 103 4>,
0205                     <0 104 4>,
0206                     <0 105 4>;
0207               };
0208           };
0209       };
0210 
0211 ...