0001 .. _hugetlbpage_index:
0002
0003 ====================
0004 HugeTLBpage on ARM64
0005 ====================
0006
0007 Hugepage relies on making efficient use of TLBs to improve performance of
0008 address translations. The benefit depends on both -
0009
0010 - the size of hugepages
0011 - size of entries supported by the TLBs
0012
0013 The ARM64 port supports two flavours of hugepages.
0014
0015 1) Block mappings at the pud/pmd level
0016 --------------------------------------
0017
0018 These are regular hugepages where a pmd or a pud page table entry points to a
0019 block of memory. Regardless of the supported size of entries in TLB, block
0020 mappings reduce the depth of page table walk needed to translate hugepage
0021 addresses.
0022
0023 2) Using the Contiguous bit
0024 ---------------------------
0025
0026 The architecture provides a contiguous bit in the translation table entries
0027 (D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a
0028 contiguous set of entries that can be cached in a single TLB entry.
0029
0030 The contiguous bit is used in Linux to increase the mapping size at the pmd and
0031 pte (last) level. The number of supported contiguous entries varies by page size
0032 and level of the page table.
0033
0034
0035 The following hugepage sizes are supported -
0036
0037 ====== ======== ==== ======== ===
0038 - CONT PTE PMD CONT PMD PUD
0039 ====== ======== ==== ======== ===
0040 4K: 64K 2M 32M 1G
0041 16K: 2M 32M 1G
0042 64K: 2M 512M 16G
0043 ====== ======== ==== ======== ===
