0001 ===========================
0002 ARM64 CPU Feature Registers
0003 ===========================
0004
0005 Author: Suzuki K Poulose <suzuki.poulose@arm.com>
0006
0007
0008 This file describes the ABI for exporting the AArch64 CPU ID/feature
0009 registers to userspace. The availability of this ABI is advertised
0010 via the HWCAP_CPUID in HWCAPs.
0011
0012 1. Motivation
0013 -------------
0014
0015 The ARM architecture defines a set of feature registers, which describe
0016 the capabilities of the CPU/system. Access to these system registers is
0017 restricted from EL0 and there is no reliable way for an application to
0018 extract this information to make better decisions at runtime. There is
0019 limited information available to the application via HWCAPs, however
0020 there are some issues with their usage.
0021
0022 a) Any change to the HWCAPs requires an update to userspace (e.g libc)
0023 to detect the new changes, which can take a long time to appear in
0024 distributions. Exposing the registers allows applications to get the
0025 information without requiring updates to the toolchains.
0026
0027 b) Access to HWCAPs is sometimes limited (e.g prior to libc, or
0028 when ld is initialised at startup time).
0029
0030 c) HWCAPs cannot represent non-boolean information effectively. The
0031 architecture defines a canonical format for representing features
0032 in the ID registers; this is well defined and is capable of
0033 representing all valid architecture variations.
0034
0035
0036 2. Requirements
0037 ---------------
0038
0039 a) Safety:
0040
0041 Applications should be able to use the information provided by the
0042 infrastructure to run safely across the system. This has greater
0043 implications on a system with heterogeneous CPUs.
0044 The infrastructure exports a value that is safe across all the
0045 available CPU on the system.
0046
0047 e.g, If at least one CPU doesn't implement CRC32 instructions, while
0048 others do, we should report that the CRC32 is not implemented.
0049 Otherwise an application could crash when scheduled on the CPU
0050 which doesn't support CRC32.
0051
0052 b) Security:
0053
0054 Applications should only be able to receive information that is
0055 relevant to the normal operation in userspace. Hence, some of the
0056 fields are masked out(i.e, made invisible) and their values are set to
0057 indicate the feature is 'not supported'. See Section 4 for the list
0058 of visible features. Also, the kernel may manipulate the fields
0059 based on what it supports. e.g, If FP is not supported by the
0060 kernel, the values could indicate that the FP is not available
0061 (even when the CPU provides it).
0062
0063 c) Implementation Defined Features
0064
0065 The infrastructure doesn't expose any register which is
0066 IMPLEMENTATION DEFINED as per ARMv8-A Architecture.
0067
0068 d) CPU Identification:
0069
0070 MIDR_EL1 is exposed to help identify the processor. On a
0071 heterogeneous system, this could be racy (just like getcpu()). The
0072 process could be migrated to another CPU by the time it uses the
0073 register value, unless the CPU affinity is set. Hence, there is no
0074 guarantee that the value reflects the processor that it is
0075 currently executing on. The REVIDR is not exposed due to this
0076 constraint, as REVIDR makes sense only in conjunction with the
0077 MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs
0078 at::
0079
0080 /sys/devices/system/cpu/cpu$ID/regs/identification/
0081 \- midr
0082 \- revidr
0083
0084 3. Implementation
0085 --------------------
0086
0087 The infrastructure is built on the emulation of the 'MRS' instruction.
0088 Accessing a restricted system register from an application generates an
0089 exception and ends up in SIGILL being delivered to the process.
0090 The infrastructure hooks into the exception handler and emulates the
0091 operation if the source belongs to the supported system register space.
0092
0093 The infrastructure emulates only the following system register space::
0094
0095 Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7
0096
0097 (See Table C5-6 'System instruction encodings for non-Debug System
0098 register accesses' in ARMv8 ARM DDI 0487A.h, for the list of
0099 registers).
0100
0101 The following rules are applied to the value returned by the
0102 infrastructure:
0103
0104 a) The value of an 'IMPLEMENTATION DEFINED' field is set to 0.
0105 b) The value of a reserved field is populated with the reserved
0106 value as defined by the architecture.
0107 c) The value of a 'visible' field holds the system wide safe value
0108 for the particular feature (except for MIDR_EL1, see section 4).
0109 d) All other fields (i.e, invisible fields) are set to indicate
0110 the feature is missing (as defined by the architecture).
0111
0112 4. List of registers with visible features
0113 -------------------------------------------
0114
0115 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
0116
0117 +------------------------------+---------+---------+
0118 | Name | bits | visible |
0119 +------------------------------+---------+---------+
0120 | RNDR | [63-60] | y |
0121 +------------------------------+---------+---------+
0122 | TS | [55-52] | y |
0123 +------------------------------+---------+---------+
0124 | FHM | [51-48] | y |
0125 +------------------------------+---------+---------+
0126 | DP | [47-44] | y |
0127 +------------------------------+---------+---------+
0128 | SM4 | [43-40] | y |
0129 +------------------------------+---------+---------+
0130 | SM3 | [39-36] | y |
0131 +------------------------------+---------+---------+
0132 | SHA3 | [35-32] | y |
0133 +------------------------------+---------+---------+
0134 | RDM | [31-28] | y |
0135 +------------------------------+---------+---------+
0136 | ATOMICS | [23-20] | y |
0137 +------------------------------+---------+---------+
0138 | CRC32 | [19-16] | y |
0139 +------------------------------+---------+---------+
0140 | SHA2 | [15-12] | y |
0141 +------------------------------+---------+---------+
0142 | SHA1 | [11-8] | y |
0143 +------------------------------+---------+---------+
0144 | AES | [7-4] | y |
0145 +------------------------------+---------+---------+
0146
0147
0148 2) ID_AA64PFR0_EL1 - Processor Feature Register 0
0149
0150 +------------------------------+---------+---------+
0151 | Name | bits | visible |
0152 +------------------------------+---------+---------+
0153 | DIT | [51-48] | y |
0154 +------------------------------+---------+---------+
0155 | SVE | [35-32] | y |
0156 +------------------------------+---------+---------+
0157 | GIC | [27-24] | n |
0158 +------------------------------+---------+---------+
0159 | AdvSIMD | [23-20] | y |
0160 +------------------------------+---------+---------+
0161 | FP | [19-16] | y |
0162 +------------------------------+---------+---------+
0163 | EL3 | [15-12] | n |
0164 +------------------------------+---------+---------+
0165 | EL2 | [11-8] | n |
0166 +------------------------------+---------+---------+
0167 | EL1 | [7-4] | n |
0168 +------------------------------+---------+---------+
0169 | EL0 | [3-0] | n |
0170 +------------------------------+---------+---------+
0171
0172
0173 3) ID_AA64PFR1_EL1 - Processor Feature Register 1
0174
0175 +------------------------------+---------+---------+
0176 | Name | bits | visible |
0177 +------------------------------+---------+---------+
0178 | MTE | [11-8] | y |
0179 +------------------------------+---------+---------+
0180 | SSBS | [7-4] | y |
0181 +------------------------------+---------+---------+
0182 | BT | [3-0] | y |
0183 +------------------------------+---------+---------+
0184
0185
0186 4) MIDR_EL1 - Main ID Register
0187
0188 +------------------------------+---------+---------+
0189 | Name | bits | visible |
0190 +------------------------------+---------+---------+
0191 | Implementer | [31-24] | y |
0192 +------------------------------+---------+---------+
0193 | Variant | [23-20] | y |
0194 +------------------------------+---------+---------+
0195 | Architecture | [19-16] | y |
0196 +------------------------------+---------+---------+
0197 | PartNum | [15-4] | y |
0198 +------------------------------+---------+---------+
0199 | Revision | [3-0] | y |
0200 +------------------------------+---------+---------+
0201
0202 NOTE: The 'visible' fields of MIDR_EL1 will contain the value
0203 as available on the CPU where it is fetched and is not a system
0204 wide safe value.
0205
0206 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
0207
0208 +------------------------------+---------+---------+
0209 | Name | bits | visible |
0210 +------------------------------+---------+---------+
0211 | I8MM | [55-52] | y |
0212 +------------------------------+---------+---------+
0213 | DGH | [51-48] | y |
0214 +------------------------------+---------+---------+
0215 | BF16 | [47-44] | y |
0216 +------------------------------+---------+---------+
0217 | SB | [39-36] | y |
0218 +------------------------------+---------+---------+
0219 | FRINTTS | [35-32] | y |
0220 +------------------------------+---------+---------+
0221 | GPI | [31-28] | y |
0222 +------------------------------+---------+---------+
0223 | GPA | [27-24] | y |
0224 +------------------------------+---------+---------+
0225 | LRCPC | [23-20] | y |
0226 +------------------------------+---------+---------+
0227 | FCMA | [19-16] | y |
0228 +------------------------------+---------+---------+
0229 | JSCVT | [15-12] | y |
0230 +------------------------------+---------+---------+
0231 | API | [11-8] | y |
0232 +------------------------------+---------+---------+
0233 | APA | [7-4] | y |
0234 +------------------------------+---------+---------+
0235 | DPB | [3-0] | y |
0236 +------------------------------+---------+---------+
0237
0238 6) ID_AA64MMFR0_EL1 - Memory model feature register 0
0239
0240 +------------------------------+---------+---------+
0241 | Name | bits | visible |
0242 +------------------------------+---------+---------+
0243 | ECV | [63-60] | y |
0244 +------------------------------+---------+---------+
0245
0246 7) ID_AA64MMFR2_EL1 - Memory model feature register 2
0247
0248 +------------------------------+---------+---------+
0249 | Name | bits | visible |
0250 +------------------------------+---------+---------+
0251 | AT | [35-32] | y |
0252 +------------------------------+---------+---------+
0253
0254 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0
0255
0256 +------------------------------+---------+---------+
0257 | Name | bits | visible |
0258 +------------------------------+---------+---------+
0259 | F64MM | [59-56] | y |
0260 +------------------------------+---------+---------+
0261 | F32MM | [55-52] | y |
0262 +------------------------------+---------+---------+
0263 | I8MM | [47-44] | y |
0264 +------------------------------+---------+---------+
0265 | SM4 | [43-40] | y |
0266 +------------------------------+---------+---------+
0267 | SHA3 | [35-32] | y |
0268 +------------------------------+---------+---------+
0269 | BF16 | [23-20] | y |
0270 +------------------------------+---------+---------+
0271 | BitPerm | [19-16] | y |
0272 +------------------------------+---------+---------+
0273 | AES | [7-4] | y |
0274 +------------------------------+---------+---------+
0275 | SVEVer | [3-0] | y |
0276 +------------------------------+---------+---------+
0277
0278 8) ID_AA64MMFR1_EL1 - Memory model feature register 1
0279
0280 +------------------------------+---------+---------+
0281 | Name | bits | visible |
0282 +------------------------------+---------+---------+
0283 | AFP | [47-44] | y |
0284 +------------------------------+---------+---------+
0285
0286 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
0287
0288 +------------------------------+---------+---------+
0289 | Name | bits | visible |
0290 +------------------------------+---------+---------+
0291 | RPRES | [7-4] | y |
0292 +------------------------------+---------+---------+
0293 | WFXT | [3-0] | y |
0294 +------------------------------+---------+---------+
0295
0296
0297 Appendix I: Example
0298 -------------------
0299
0300 ::
0301
0302 /*
0303 * Sample program to demonstrate the MRS emulation ABI.
0304 *
0305 * Copyright (C) 2015-2016, ARM Ltd
0306 *
0307 * Author: Suzuki K Poulose <suzuki.poulose@arm.com>
0308 *
0309 * This program is free software; you can redistribute it and/or modify
0310 * it under the terms of the GNU General Public License version 2 as
0311 * published by the Free Software Foundation.
0312 *
0313 * This program is distributed in the hope that it will be useful,
0314 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0315 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0316 * GNU General Public License for more details.
0317 * This program is free software; you can redistribute it and/or modify
0318 * it under the terms of the GNU General Public License version 2 as
0319 * published by the Free Software Foundation.
0320 *
0321 * This program is distributed in the hope that it will be useful,
0322 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0323 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0324 * GNU General Public License for more details.
0325 */
0326
0327 #include <asm/hwcap.h>
0328 #include <stdio.h>
0329 #include <sys/auxv.h>
0330
0331 #define get_cpu_ftr(id) ({ \
0332 unsigned long __val; \
0333 asm("mrs %0, "#id : "=r" (__val)); \
0334 printf("%-20s: 0x%016lx\n", #id, __val); \
0335 })
0336
0337 int main(void)
0338 {
0339
0340 if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) {
0341 fputs("CPUID registers unavailable\n", stderr);
0342 return 1;
0343 }
0344
0345 get_cpu_ftr(ID_AA64ISAR0_EL1);
0346 get_cpu_ftr(ID_AA64ISAR1_EL1);
0347 get_cpu_ftr(ID_AA64MMFR0_EL1);
0348 get_cpu_ftr(ID_AA64MMFR1_EL1);
0349 get_cpu_ftr(ID_AA64PFR0_EL1);
0350 get_cpu_ftr(ID_AA64PFR1_EL1);
0351 get_cpu_ftr(ID_AA64DFR0_EL1);
0352 get_cpu_ftr(ID_AA64DFR1_EL1);
0353
0354 get_cpu_ftr(MIDR_EL1);
0355 get_cpu_ftr(MPIDR_EL1);
0356 get_cpu_ftr(REVIDR_EL1);
0357
0358 #if 0
0359 /* Unexposed register access causes SIGILL */
0360 get_cpu_ftr(ID_MMFR0_EL1);
0361 #endif
0362
0363 return 0;
0364 }
