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0004 Activity Monitors Unit (AMU) extension in AArch64 Linux
0005 =======================================================
0006
0007 Author: Ionela Voinescu <ionela.voinescu@arm.com>
0008
0009 Date: 2019-09-10
0010
0011 This document briefly describes the provision of Activity Monitors Unit
0012 support in AArch64 Linux.
0013
0014
0015 Architecture overview
0016 ---------------------
0017
0018 The activity monitors extension is an optional extension introduced by the
0019 ARMv8.4 CPU architecture.
0020
0021 The activity monitors unit, implemented in each CPU, provides performance
0022 counters intended for system management use. The AMU extension provides a
0023 system register interface to the counter registers and also supports an
0024 optional external memory-mapped interface.
0025
0026 Version 1 of the Activity Monitors architecture implements a counter group
0027 of four fixed and architecturally defined 64-bit event counters.
0028
0029 - CPU cycle counter: increments at the frequency of the CPU.
0030 - Constant counter: increments at the fixed frequency of the system
0031 clock.
0032 - Instructions retired: increments with every architecturally executed
0033 instruction.
0034 - Memory stall cycles: counts instruction dispatch stall cycles caused by
0035 misses in the last level cache within the clock domain.
0036
0037 When in WFI or WFE these counters do not increment.
0038
0039 The Activity Monitors architecture provides space for up to 16 architected
0040 event counters. Future versions of the architecture may use this space to
0041 implement additional architected event counters.
0042
0043 Additionally, version 1 implements a counter group of up to 16 auxiliary
0044 64-bit event counters.
0045
0046 On cold reset all counters reset to 0.
0047
0048
0049 Basic support
0050 -------------
0051
0052 The kernel can safely run a mix of CPUs with and without support for the
0053 activity monitors extension. Therefore, when CONFIG_ARM64_AMU_EXTN is
0054 selected we unconditionally enable the capability to allow any late CPU
0055 (secondary or hotplugged) to detect and use the feature.
0056
0057 When the feature is detected on a CPU, we flag the availability of the
0058 feature but this does not guarantee the correct functionality of the
0059 counters, only the presence of the extension.
0060
0061 Firmware (code running at higher exception levels, e.g. arm-tf) support is
0062 needed to:
0063
0064 - Enable access for lower exception levels (EL2 and EL1) to the AMU
0065 registers.
0066 - Enable the counters. If not enabled these will read as 0.
0067 - Save/restore the counters before/after the CPU is being put/brought up
0068 from the 'off' power state.
0069
0070 When using kernels that have this feature enabled but boot with broken
0071 firmware the user may experience panics or lockups when accessing the
0072 counter registers. Even if these symptoms are not observed, the values
0073 returned by the register reads might not correctly reflect reality. Most
0074 commonly, the counters will read as 0, indicating that they are not
0075 enabled.
0076
0077 If proper support is not provided in firmware it's best to disable
0078 CONFIG_ARM64_AMU_EXTN. To be noted that for security reasons, this does not
0079 bypass the setting of AMUSERENR_EL0 to trap accesses from EL0 (userspace) to
0080 EL1 (kernel). Therefore, firmware should still ensure accesses to AMU registers
0081 are not trapped in EL2/EL3.
0082
0083 The fixed counters of AMUv1 are accessible though the following system
0084 register definitions:
0085
0086 - SYS_AMEVCNTR0_CORE_EL0
0087 - SYS_AMEVCNTR0_CONST_EL0
0088 - SYS_AMEVCNTR0_INST_RET_EL0
0089 - SYS_AMEVCNTR0_MEM_STALL_EL0
0090
0091 Auxiliary platform specific counters can be accessed using
0092 SYS_AMEVCNTR1_EL0(n), where n is a value between 0 and 15.
0093
0094 Details can be found in: arch/arm64/include/asm/sysreg.h.
0095
0096
0097 Userspace access
0098 ----------------
0099
0100 Currently, access from userspace to the AMU registers is disabled due to:
0101
0102 - Security reasons: they might expose information about code executed in
0103 secure mode.
0104 - Purpose: AMU counters are intended for system management use.
0105
0106 Also, the presence of the feature is not visible to userspace.
0107
0108
0109 Virtualization
0110 --------------
0111
0112 Currently, access from userspace (EL0) and kernelspace (EL1) on the KVM
0113 guest side is disabled due to:
0114
0115 - Security reasons: they might expose information about code executed
0116 by other guests or the host.
0117
0118 Any attempt to access the AMU registers will result in an UNDEFINED
0119 exception being injected into the guest.
