0001 Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE)
0002 ---------------------------------------------------------------------
0003
0004 ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds
0005 moving to the load-locked/store-conditional instructions LDREX and STREX.
0006
0007 ARMv7 multiprocessing extensions introduce the ability to disable these
0008 instructions, triggering an undefined instruction exception when executed.
0009 Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB
0010 sequence. If a memory access fault (an abort) occurs, a segmentation fault is
0011 signalled to the triggering process.
0012
0013 /proc/cpu/swp_emulation holds some statistics/information, including the PID of
0014 the last process to trigger the emulation to be invocated. For example::
0015
0016 Emulated SWP: 12
0017 Emulated SWPB: 0
0018 Aborted SWP{B}: 1
0019 Last process: 314
0020
0021
0022 NOTE:
0023 when accessing uncached shared regions, LDREX/STREX rely on an external
0024 transaction monitoring block called a global monitor to maintain update
0025 atomicity. If your system does not implement a global monitor, this option can
0026 cause programs that perform SWP operations to uncached memory to deadlock, as
0027 the STREX operation will always fail.
