0001 .. SPDX-License-Identifier: GPL-2.0-only
0002
0003 =======================
0004 S3C24XX CPUfreq support
0005 =======================
0006
0007 Introduction
0008 ------------
0009
0010 The S3C24XX series support a number of power saving systems, such as
0011 the ability to change the core, memory and peripheral operating
0012 frequencies. The core control is exported via the CPUFreq driver
0013 which has a number of different manual or automatic controls over the
0014 rate the core is running at.
0015
0016 There are two forms of the driver depending on the specific CPU and
0017 how the clocks are arranged. The first implementation used as single
0018 PLL to feed the ARM, memory and peripherals via a series of dividers
0019 and muxes and this is the implementation that is documented here. A
0020 newer version where there is a separate PLL and clock divider for the
0021 ARM core is available as a separate driver.
0022
0023
0024 Layout
0025 ------
0026
0027 The code core manages the CPU specific drivers, any data that they
0028 need to register and the interface to the generic drivers/cpufreq
0029 system. Each CPU registers a driver to control the PLL, clock dividers
0030 and anything else associated with it. Any board that wants to use this
0031 framework needs to supply at least basic details of what is required.
0032
0033 The core registers with drivers/cpufreq at init time if all the data
0034 necessary has been supplied.
0035
0036
0037 CPU support
0038 -----------
0039
0040 The support for each CPU depends on the facilities provided by the
0041 SoC and the driver as each device has different PLL and clock chains
0042 associated with it.
0043
0044
0045 Slow Mode
0046 ---------
0047
0048 The SLOW mode where the PLL is turned off altogether and the
0049 system is fed by the external crystal input is currently not
0050 supported.
0051
0052
0053 sysfs
0054 -----
0055
0056 The core code exports extra information via sysfs in the directory
0057 devices/system/cpu/cpu0/arch-freq.
0058
0059
0060 Board Support
0061 -------------
0062
0063 Each board that wants to use the cpufreq code must register some basic
0064 information with the core driver to provide information about what the
0065 board requires and any restrictions being placed on it.
0066
0067 The board needs to supply information about whether it needs the IO bank
0068 timings changing, any maximum frequency limits and information about the
0069 SDRAM refresh rate.
0070
0071
0072
0073
0074 Document Author
0075 ---------------
0076
0077 Ben Dooks, Copyright 2009 Simtec Electronics
