0001 ==============================================
0002 MFP Configuration for PXA2xx/PXA3xx Processors
0003 ==============================================
0004
0005 Eric Miao <eric.miao@marvell.com>
0006
0007 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
0008 later PXA series processors. This document describes the existing MFP API,
0009 and how board/platform driver authors could make use of it.
0010
0011 Basic Concept
0012 =============
0013
0014 Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
0015 mechanism is introduced from PXA3xx to completely move the pin-mux functions
0016 out of the GPIO controller. In addition to pin-mux configurations, the MFP
0017 also controls the low power state, driving strength, pull-up/down and event
0018 detection of each pin. Below is a diagram of internal connections between
0019 the MFP logic and the remaining SoC peripherals::
0020
0021 +--------+
0022 | |--(GPIO19)--+
0023 | GPIO | |
0024 | |--(GPIO...) |
0025 +--------+ |
0026 | +---------+
0027 +--------+ +------>| |
0028 | PWM2 |--(PWM_OUT)-------->| MFP |
0029 +--------+ +------>| |-------> to external PAD
0030 | +---->| |
0031 +--------+ | | +-->| |
0032 | SSP2 |---(TXD)----+ | | +---------+
0033 +--------+ | |
0034 | |
0035 +--------+ | |
0036 | Keypad |--(MKOUT4)----+ |
0037 +--------+ |
0038 |
0039 +--------+ |
0040 | UART2 |---(TXD)--------+
0041 +--------+
0042
0043 NOTE: the external pad is named as MFP_PIN_GPIO19, it doesn't necessarily
0044 mean it's dedicated for GPIO19, only as a hint that internally this pin
0045 can be routed from GPIO19 of the GPIO controller.
0046
0047 To better understand the change from PXA25x/PXA27x GPIO alternate function
0048 to this new MFP mechanism, here are several key points:
0049
0050 1. GPIO controller on PXA3xx is now a dedicated controller, same as other
0051 internal controllers like PWM, SSP and UART, with 128 internal signals
0052 which can be routed to external through one or more MFPs (e.g. GPIO<0>
0053 can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2,
0054 see arch/arm/mach-pxa/mfp-pxa300.h)
0055
0056 2. Alternate function configuration is removed from this GPIO controller,
0057 the remaining functions are pure GPIO-specific, i.e.
0058
0059 - GPIO signal level control
0060 - GPIO direction control
0061 - GPIO level change detection
0062
0063 3. Low power state for each pin is now controlled by MFP, this means the
0064 PGSRx registers on PXA2xx are now useless on PXA3xx
0065
0066 4. Wakeup detection is now controlled by MFP, PWER does not control the
0067 wakeup from GPIO(s) any more, depending on the sleeping state, ADxER
0068 (as defined in pxa3xx-regs.h) controls the wakeup from MFP
0069
0070 NOTE: with such a clear separation of MFP and GPIO, by GPIO<xx> we normally
0071 mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical
0072 pad (or ball).
0073
0074 MFP API Usage
0075 =============
0076
0077 For board code writers, here are some guidelines:
0078
0079 1. include ONE of the following header files in your <board>.c:
0080
0081 - #include "mfp-pxa25x.h"
0082 - #include "mfp-pxa27x.h"
0083 - #include "mfp-pxa300.h"
0084 - #include "mfp-pxa320.h"
0085 - #include "mfp-pxa930.h"
0086
0087 NOTE: only one file in your <board>.c, depending on the processors used,
0088 because pin configuration definitions may conflict in these file (i.e.
0089 same name, different meaning and settings on different processors). E.g.
0090 for zylonite platform, which support both PXA300/PXA310 and PXA320, two
0091 separate files are introduced: zylonite_pxa300.c and zylonite_pxa320.c
0092 (in addition to handle MFP configuration differences, they also handle
0093 the other differences between the two combinations).
0094
0095 NOTE: PXA300 and PXA310 are almost identical in pin configurations (with
0096 PXA310 supporting some additional ones), thus the difference is actually
0097 covered in a single mfp-pxa300.h.
0098
0099 2. prepare an array for the initial pin configurations, e.g.::
0100
0101 static unsigned long mainstone_pin_config[] __initdata = {
0102 /* Chip Select */
0103 GPIO15_nCS_1,
0104
0105 /* LCD - 16bpp Active TFT */
0106 GPIOxx_TFT_LCD_16BPP,
0107 GPIO16_PWM0_OUT, /* Backlight */
0108
0109 /* MMC */
0110 GPIO32_MMC_CLK,
0111 GPIO112_MMC_CMD,
0112 GPIO92_MMC_DAT_0,
0113 GPIO109_MMC_DAT_1,
0114 GPIO110_MMC_DAT_2,
0115 GPIO111_MMC_DAT_3,
0116
0117 ...
0118
0119 /* GPIO */
0120 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
0121 };
0122
0123 a) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(),
0124 and written to the actual registers, they are useless and may discard,
0125 adding '__initdata' will help save some additional bytes here.
0126
0127 b) when there is only one possible pin configurations for a component,
0128 some simplified definitions can be used, e.g. GPIOxx_TFT_LCD_16BPP on
0129 PXA25x and PXA27x processors
0130
0131 c) if by board design, a pin can be configured to wake up the system
0132 from low power state, it can be 'OR'ed with any of:
0133
0134 WAKEUP_ON_EDGE_BOTH
0135 WAKEUP_ON_EDGE_RISE
0136 WAKEUP_ON_EDGE_FALL
0137 WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs,
0138
0139 to indicate that this pin has the capability of wake-up the system,
0140 and on which edge(s). This, however, doesn't necessarily mean the
0141 pin _will_ wakeup the system, it will only when set_irq_wake() is
0142 invoked with the corresponding GPIO IRQ (GPIO_IRQ(xx) or gpio_to_irq())
0143 and eventually calls gpio_set_wake() for the actual register setting.
0144
0145 d) although PXA3xx MFP supports edge detection on each pin, the
0146 internal logic will only wakeup the system when those specific bits
0147 in ADxER registers are set, which can be well mapped to the
0148 corresponding peripheral, thus set_irq_wake() can be called with
0149 the peripheral IRQ to enable the wakeup.
0150
0151
0152 MFP on PXA3xx
0153 =============
0154
0155 Every external I/O pad on PXA3xx (excluding those for special purpose) has
0156 one MFP logic associated, and is controlled by one MFP register (MFPR).
0157
0158 The MFPR has the following bit definitions (for PXA300/PXA310/PXA320)::
0159
0160 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0161 +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
0162 | RESERVED |PS|PU|PD| DRIVE |SS|SD|SO|EC|EF|ER|--| AF_SEL |
0163 +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
0164
0165 Bit 3: RESERVED
0166 Bit 4: EDGE_RISE_EN - enable detection of rising edge on this pin
0167 Bit 5: EDGE_FALL_EN - enable detection of falling edge on this pin
0168 Bit 6: EDGE_CLEAR - disable edge detection on this pin
0169 Bit 7: SLEEP_OE_N - enable outputs during low power modes
0170 Bit 8: SLEEP_DATA - output data on the pin during low power modes
0171 Bit 9: SLEEP_SEL - selection control for low power modes signals
0172 Bit 13: PULLDOWN_EN - enable the internal pull-down resistor on this pin
0173 Bit 14: PULLUP_EN - enable the internal pull-up resistor on this pin
0174 Bit 15: PULL_SEL - pull state controlled by selected alternate function
0175 (0) or by PULL{UP,DOWN}_EN bits (1)
0176
0177 Bit 0 - 2: AF_SEL - alternate function selection, 8 possibilities, from 0-7
0178 Bit 10-12: DRIVE - drive strength and slew rate
0179 0b000 - fast 1mA
0180 0b001 - fast 2mA
0181 0b002 - fast 3mA
0182 0b003 - fast 4mA
0183 0b004 - slow 6mA
0184 0b005 - fast 6mA
0185 0b006 - slow 10mA
0186 0b007 - fast 10mA
0187
0188 MFP Design for PXA2xx/PXA3xx
0189 ============================
0190
0191 Due to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified
0192 MFP API is introduced to cover both series of processors.
0193
0194 The basic idea of this design is to introduce definitions for all possible pin
0195 configurations, these definitions are processor and platform independent, and
0196 the actual API invoked to convert these definitions into register settings and
0197 make them effective there-after.
0198
0199 Files Involved
0200 --------------
0201
0202 - arch/arm/mach-pxa/include/mach/mfp.h
0203
0204 for
0205 1. Unified pin definitions - enum constants for all configurable pins
0206 2. processor-neutral bit definitions for a possible MFP configuration
0207
0208 - arch/arm/mach-pxa/mfp-pxa3xx.h
0209
0210 for PXA3xx specific MFPR register bit definitions and PXA3xx common pin
0211 configurations
0212
0213 - arch/arm/mach-pxa/mfp-pxa2xx.h
0214
0215 for PXA2xx specific definitions and PXA25x/PXA27x common pin configurations
0216
0217 - arch/arm/mach-pxa/mfp-pxa25x.h
0218 arch/arm/mach-pxa/mfp-pxa27x.h
0219 arch/arm/mach-pxa/mfp-pxa300.h
0220 arch/arm/mach-pxa/mfp-pxa320.h
0221 arch/arm/mach-pxa/mfp-pxa930.h
0222
0223 for processor specific definitions
0224
0225 - arch/arm/mach-pxa/mfp-pxa3xx.c
0226 - arch/arm/mach-pxa/mfp-pxa2xx.c
0227
0228 for implementation of the pin configuration to take effect for the actual
0229 processor.
0230
0231 Pin Configuration
0232 -----------------
0233
0234 The following comments are copied from mfp.h (see the actual source code
0235 for most updated info)::
0236
0237 /*
0238 * a possible MFP configuration is represented by a 32-bit integer
0239 *
0240 * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
0241 * bit 10..12 - Alternate Function Selection
0242 * bit 13..15 - Drive Strength
0243 * bit 16..18 - Low Power Mode State
0244 * bit 19..20 - Low Power Mode Edge Detection
0245 * bit 21..22 - Run Mode Pull State
0246 *
0247 * to facilitate the definition, the following macros are provided
0248 *
0249 * MFP_CFG_DEFAULT - default MFP configuration value, with
0250 * alternate function = 0,
0251 * drive strength = fast 3mA (MFP_DS03X)
0252 * low power mode = default
0253 * edge detection = none
0254 *
0255 * MFP_CFG - default MFPR value with alternate function
0256 * MFP_CFG_DRV - default MFPR value with alternate function and
0257 * pin drive strength
0258 * MFP_CFG_LPM - default MFPR value with alternate function and
0259 * low power mode
0260 * MFP_CFG_X - default MFPR value with alternate function,
0261 * pin drive strength and low power mode
0262 */
0263
0264 Examples of pin configurations are::
0265
0266 #define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
0267
0268 which reads GPIO94 can be configured as SSP3_RXD, with alternate function
0269 selection of 1, driving strength of 0b101, and a float state in low power
0270 modes.
0271
0272 NOTE: this is the default setting of this pin being configured as SSP3_RXD
0273 which can be modified a bit in board code, though it is not recommended to
0274 do so, simply because this default setting is usually carefully encoded,
0275 and is supposed to work in most cases.
0276
0277 Register Settings
0278 -----------------
0279
0280 Register settings on PXA3xx for a pin configuration is actually very
0281 straight-forward, most bits can be converted directly into MFPR value
0282 in a easier way. Two sets of MFPR values are calculated: the run-time
0283 ones and the low power mode ones, to allow different settings.
0284
0285 The conversion from a generic pin configuration to the actual register
0286 settings on PXA2xx is a bit complicated: many registers are involved,
0287 including GAFRx, GPDRx, PGSRx, PWER, PKWR, PFER and PRER. Please see
0288 mfp-pxa2xx.c for how the conversion is made.
