0001 =============================================================
0002 Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE)
0003 =============================================================
0004
0005 The ThunderX2 SoC PMU consists of independent, system-wide, per-socket
0006 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
0007 Cavium Coherent Processor Interconnect (CCPI2).
0008
0009 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
0010 Events are counted for the default channel (i.e. channel 0) and prorated
0011 to the total number of channels/tiles.
0012
0013 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
0014 counters. Counters are independently programmable to different events and
0015 can be started and stopped individually. None of the counters support an
0016 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
0017 The CCPI2 counters are 64-bit and assumed not to overflow in normal operation.
0018
0019 PMU UNCORE (perf) driver:
0020
0021 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
0022 L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
0023 (CCPI2) events simultaneously. The PMUs provide a description of their
0024 available events and configuration options under sysfs, see
0025 /sys/devices/uncore_<l3c_S/dmc_S/ccpi2_S/>; S is the socket id.
0026
0027 The driver does not support sampling, therefore "perf record" will not
0028 work. Per-task perf sessions are also not supported.
0029
0030 Examples::
0031
0032 # perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1
0033
0034 # perf stat -a -e \
0035 uncore_dmc_0/cnt_cycles/,\
0036 uncore_dmc_0/data_transfers/,\
0037 uncore_dmc_0/read_txns/,\
0038 uncore_dmc_0/write_txns/ sleep 1
0039
0040 # perf stat -a -e \
0041 uncore_l3c_0/read_request/,\
0042 uncore_l3c_0/read_hit/,\
0043 uncore_l3c_0/inv_request/,\
0044 uncore_l3c_0/inv_hit/ sleep 1
