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0002 Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
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0004
0005 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
0006 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
0007 by all cores within a socket. Each slice is exposed as a separate uncore perf
0008 PMU with device name l3cache_<socket>_<instance>. User space is responsible
0009 for aggregating across slices.
0010
0011 The driver provides a description of its available events and configuration
0012 options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs
0013 the driver also exposes a "cpumask" sysfs attribute which contains a mask
0014 consisting of one CPU per socket which will be used to handle all the PMU
0015 events on that socket.
0016
0017 The hardware implements 32bit event counters and has a flat 8bit event space
0018 exposed via the "event" format attribute. In addition to the 32bit physical
0019 counters the driver supports virtual 64bit hardware counters by using hardware
0020 counter chaining. This feature is exposed via the "lc" (long counter) format
0021 flag. E.g.::
0022
0023 perf stat -e l3cache_0_0/read-miss,lc/
0024
0025 Given that these are uncore PMUs the driver does not support sampling, therefore
0026 "perf record" will not work. Per-task perf sessions are not supported.
