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0002 Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU)
0003 =====================================================================
0004
0005 This driver supports the L2 cache clusters found in Qualcomm Technologies
0006 Centriq SoCs. There are multiple physical L2 cache clusters, each with their
0007 own PMU. Each cluster has one or more CPUs associated with it.
0008
0009 There is one logical L2 PMU exposed, which aggregates the results from
0010 the physical PMUs.
0011
0012 The driver provides a description of its available events and configuration
0013 options in sysfs, see /sys/devices/l2cache_0.
0014
0015 The "format" directory describes the format of the events.
0016
0017 Events can be envisioned as a 2-dimensional array. Each column represents
0018 a group of events. There are 8 groups. Only one entry from each
0019 group can be in use at a time. If multiple events from the same group
0020 are specified, the conflicting events cannot be counted at the same time.
0021
0022 Events are specified as 0xCCG, where CC is 2 hex digits specifying
0023 the code (array row) and G specifies the group (column) 0-7.
0024
0025 In addition there is a cycle counter event specified by the value 0xFE
0026 which is outside the above scheme.
0027
0028 The driver provides a "cpumask" sysfs attribute which contains a mask
0029 consisting of one CPU per cluster which will be used to handle all the PMU
0030 events on that cluster.
0031
0032 Examples for use with perf::
0033
0034 perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1
0035
0036 perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1
0037
0038 The driver does not support sampling, therefore "perf record" will
0039 not work. Per-task perf sessions are not supported.
