0001 =====================================================
0002 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
0003 =====================================================
0004
0005 There are no performance counters inside the DRAM controller, so performance
0006 signals are brought out to the edge of the controller where a set of 4 x 32 bit
0007 counters is implemented. This is controlled by the CSV modes programmed in counter
0008 control register which causes a large number of PERF signals to be generated.
0009
0010 Selection of the value for each counter is done via the config registers. There
0011 is one register for each counter. Counter 0 is special in that it always counts
0012 “time” and when expired causes a lock on itself and the other counters and an
0013 interrupt is raised. If any other counter overflows, it continues counting, and
0014 no interrupt is raised.
0015
0016 The "format" directory describes format of the config (event ID) and config1
0017 (AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/
0018 devices/imx8_ddr0/format/. The "events" directory describes the events types
0019 hardware supported that can be used with perf tool, see /sys/bus/event_source/
0020 devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented
0021 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
0022
0023 .. code-block:: bash
0024
0025 perf stat -a -e imx8_ddr0/cycles/ cmd
0026 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
0027
0028 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
0029 to count reading or writing matches filter setting. Filter setting is various
0030 from different DRAM controller implementations, which is distinguished by quirks
0031 in the driver. You also can dump info from userspace, filter in "caps" directory
0032 indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
0033 whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
0034 value 1 for supported.
0035
0036 * With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0).
0037 Filter is defined with two configuration parts:
0038 --AXI_ID defines AxID matching value.
0039 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
0040
0041 - 0: corresponding bit is masked.
0042 - 1: corresponding bit is not masked, i.e. used to do the matching.
0043
0044 AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter.
0045 When non-masked bits are matching corresponding AXI_ID bits then counter is
0046 incremented. Perf counter is incremented if::
0047
0048 AxID && AXI_MASKING == AXI_ID && AXI_MASKING
0049
0050 This filter doesn't support filter different AXI ID for axid-read and axid-write
0051 event at the same time as this filter is shared between counters.
0052
0053 .. code-block:: bash
0054
0055 perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
0056 perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
0057
0058 .. note::
0059
0060 axi_mask is inverted in userspace(i.e. set bits are bits to mask), and
0061 it will be reverted in driver automatically. so that the user can just specify
0062 axi_id to monitor a specific id, rather than having to specify axi_mask.
0063
0064 .. code-block:: bash
0065
0066 perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12
0067
0068 * With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1).
0069 This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits
0070 counting the number of bytes (as opposed to the number of bursts) from DDR
0071 read and write transactions concurrently with another set of data counters.
